From patchwork Wed Apr 20 11:06:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhengxing X-Patchwork-Id: 8888521 Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1BAFDBF29F for ; Wed, 20 Apr 2016 11:09:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2DCBC201B4 for ; Wed, 20 Apr 2016 11:08:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3E92320165 for ; Wed, 20 Apr 2016 11:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753576AbcDTLIJ (ORCPT ); Wed, 20 Apr 2016 07:08:09 -0400 Received: from regular1.263xmail.com ([211.150.99.130]:54123 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754532AbcDTLHW (ORCPT ); Wed, 20 Apr 2016 07:07:22 -0400 Received: from zhengxing?rock-chips.com (unknown [192.168.167.232]) by regular1.263xmail.com (Postfix) with SMTP id A23FCB4FC; Wed, 20 Apr 2016 19:07:14 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-KSVirus-check: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 2314E35D8; Wed, 20 Apr 2016 19:07:15 +0800 (CST) X-RL-SENDER: zhengxing@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: <8a912c79b75c05e7035120d54b5d3722> X-ATTACHMENT-NUM: 0 X-SENDER: zhengxing@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 1790A10QXQ; Wed, 20 Apr 2016 19:07:16 +0800 (CST) From: Xing Zheng To: linux-rockchip@lists.infradead.org Cc: heiko@sntech.de, huangtao@rock-chips.com, elaine.zhang@rock-chips.com, jay.xu@rock-chips.com, dianders@chromium.org, Xing Zheng , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] clk: rockchip: rk3399: update necessary critical clocks Date: Wed, 20 Apr 2016 19:06:52 +0800 Message-Id: <1461150414-29638-5-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1461150414-29638-1-git-send-email-zhengxing@rock-chips.com> References: <1461150414-29638-1-git-send-email-zhengxing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We need to declare that we enable all NOCs which are critical clocks always and clearly and explicitly show that we have enabled them at clk_summary. We need to add some has been verified and required critical clocks in the development process. And the pclk_perilp1_noc is also add CLK_IGNORE_UNUSED flag. Signed-off-by: Xing Zheng --- drivers/clk/rockchip/clk-rk3399.c | 72 +++++++++++++++++++++++++++++++------ 1 file changed, 62 insertions(+), 10 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 232ea68..1da4fe1 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1043,7 +1043,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), - GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), + GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 10, GFLAGS), /* saradc */ COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, @@ -1464,33 +1464,85 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { }; static const char *const rk3399_cru_critical_clocks[] __initconst = { - "aclk_cci_pre", + /* + * We need to declare that we enable all NOCs which are critical clocks + * always and clearly and explicitly show that we have enabled them at + * clk_summary. + */ + "aclk_usb3_noc", + "aclk_gmac_noc", + "pclk_gmac_noc", + "pclk_center_main_noc", + "aclk_cci_noc0", + "aclk_cci_noc1", + "clk_dbg_noc", + "hclk_vcodec_noc", + "aclk_vcodec_noc", + "hclk_vdu_noc", + "aclk_vdu_noc", + "hclk_iep_noc", + "aclk_iep_noc", + "hclk_rga_noc", + "aclk_rga_noc", + "aclk_center_main_noc", + "aclk_center_peri_noc", + "aclk_perihp_noc", + "hclk_perihp_noc", + "pclk_perihp_noc", + "hclk_sdmmc_noc", + "aclk_emmc_noc", + "aclk_perilp0_noc", + "hclk_perilp0_noc", + "hclk_m0_perilp_noc", + "hclk_perilp1_noc", + "hclk_sdio_noc", + "hclk_sdioaudio_noc", + "pclk_perilp1_noc", + "aclk_vio_noc", + "aclk_hdcp_noc", + "hclk_hdcp_noc", + "pclk_hdcp_noc", + "pclk_edp_noc", + "aclk_vop0_noc", + "hclk_vop0_noc", + "aclk_vop1_noc", + "hclk_vop1_noc", + "aclk_isp0_noc", + "hclk_isp0_noc", + "aclk_isp1_noc", + "hclk_isp1_noc", + "aclk_gic_noc", + + /* other critical clocks */ "pclk_perilp0", "pclk_perilp0", "hclk_perilp0", - "hclk_perilp0_noc", "pclk_perilp1", - "pclk_perilp1_noc", "pclk_perihp", - "pclk_perihp_noc", "hclk_perihp", "aclk_perihp", - "aclk_perihp_noc", "aclk_perilp0", - "aclk_perilp0_noc", "hclk_perilp1", - "hclk_perilp1_noc", - "aclk_dmac0_perilp", - "gpll_hclk_perilp1_src", + "aclk_dmac1_perilp", "gpll_aclk_perilp0_src", "gpll_aclk_perihp_src", }; static const char *const rk3399_pmucru_critical_clocks[] __initconst = { + /* + * We need to declare that we enable all NOCs which are critical clocks + * always and clearly and explicitly show that we have enabled them at + * clk_summary. + */ + "pclk_noc_pmu", + "hclk_noc_pmu", + + /* other critical clocks */ "ppll", "pclk_pmu_src", "fclk_cm0s_src_pmu", "clk_timer_src_pmu", + "pclk_rkpwm_pmu", }; static void __init rk3399_clk_init(struct device_node *np)