From patchwork Thu Apr 28 13:11:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 8970021 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E321B9F1C1 for ; Thu, 28 Apr 2016 13:11:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BBD5F202EB for ; Thu, 28 Apr 2016 13:11:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A813C202D1 for ; Thu, 28 Apr 2016 13:11:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751774AbcD1NLY (ORCPT ); Thu, 28 Apr 2016 09:11:24 -0400 Received: from gloria.sntech.de ([95.129.55.99]:40529 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751514AbcD1NLX (ORCPT ); Thu, 28 Apr 2016 09:11:23 -0400 Received: from ip9234b7c8.dynamic.kabel-deutschland.de ([146.52.183.200] helo=diego.lan) by gloria.sntech.de with esmtpsa (TLS1.1:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1avliz-0006x7-BB; Thu, 28 Apr 2016 15:11:21 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, Heiko Stuebner Subject: [PATCH 5/7] clk: rockchip: generalize pll set-rate operation Date: Thu, 28 Apr 2016 15:11:13 +0200 Message-Id: <1461849075-8310-6-git-send-email-heiko@sntech.de> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1461849075-8310-1-git-send-email-heiko@sntech.de> References: <1461849075-8310-1-git-send-email-heiko@sntech.de> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The currently pll-specific set_rate operations are now identical, and with the actual register access already being abstracted away will also stay that way. Therefore merge them into one function used by each PLL. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 86 +++++++++++------------------------------- 1 file changed, 23 insertions(+), 63 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 2c30f52..081713c 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -94,6 +94,26 @@ static long rockchip_pll_round_rate(struct clk_hw *hw, return rate_table[i - 1].rate; } +static int rockchip_pll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + + pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", + __func__, clk_hw_get_name(hw), drate, prate); + + /* Get required rate settings from table */ + rate = rockchip_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + return pll->data->set_params(pll, rate); +} + /* * Wait for the pll to reach the locked state. * The calling set_rate function is responsible for making sure the @@ -251,26 +271,6 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, return ret; } -static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - - pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw->clk), drate, prate); - - /* Get required rate settings from table */ - rate = rockchip_get_pll_settings(pll, drate); - if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); - return -EINVAL; - } - - return pll->data->set_params(pll, rate); -} - static int rockchip_rk3036_pll_enable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); @@ -358,7 +358,7 @@ static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { static const struct clk_ops rockchip_rk3036_pll_clk_ops = { .recalc_rate = rockchip_rk3036_pll_recalc_rate, .round_rate = rockchip_pll_round_rate, - .set_rate = rockchip_rk3036_pll_set_rate, + .set_rate = rockchip_pll_set_rate, .enable = rockchip_rk3036_pll_enable, .disable = rockchip_rk3036_pll_disable, .is_enabled = rockchip_rk3036_pll_is_enabled, @@ -487,26 +487,6 @@ static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, return ret; } -static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - - pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", - __func__, clk_hw_get_name(hw), drate, prate); - - /* Get required rate settings from table */ - rate = rockchip_get_pll_settings(pll, drate); - if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, clk_hw_get_name(hw)); - return -EINVAL; - } - - return pll->data->set_params(pll, rate); -} - static int rockchip_rk3066_pll_enable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); @@ -579,7 +559,7 @@ static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { static const struct clk_ops rockchip_rk3066_pll_clk_ops = { .recalc_rate = rockchip_rk3066_pll_recalc_rate, .round_rate = rockchip_pll_round_rate, - .set_rate = rockchip_rk3066_pll_set_rate, + .set_rate = rockchip_pll_set_rate, .enable = rockchip_rk3066_pll_enable, .disable = rockchip_rk3066_pll_disable, .is_enabled = rockchip_rk3066_pll_is_enabled, @@ -737,26 +717,6 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, return ret; } -static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); - const struct rockchip_pll_rate_table *rate; - - pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw->clk), drate, prate); - - /* Get required rate settings from table */ - rate = rockchip_get_pll_settings(pll, drate); - if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); - return -EINVAL; - } - - return pll->data->set_params(pll, rate); -} - static int rockchip_rk3399_pll_enable(struct clk_hw *hw) { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); @@ -844,7 +804,7 @@ static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = { static const struct clk_ops rockchip_rk3399_pll_clk_ops = { .recalc_rate = rockchip_rk3399_pll_recalc_rate, .round_rate = rockchip_pll_round_rate, - .set_rate = rockchip_rk3399_pll_set_rate, + .set_rate = rockchip_pll_set_rate, .enable = rockchip_rk3399_pll_enable, .disable = rockchip_rk3399_pll_disable, .is_enabled = rockchip_rk3399_pll_is_enabled,