From patchwork Mon May 9 12:31:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 9046001 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 567CCBF29F for ; Mon, 9 May 2016 12:32:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4BB3A20148 for ; Mon, 9 May 2016 12:32:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 45A5F2010B for ; Mon, 9 May 2016 12:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751733AbcEIMcO (ORCPT ); Mon, 9 May 2016 08:32:14 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:34950 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751702AbcEIMcN (ORCPT ); Mon, 9 May 2016 08:32:13 -0400 Received: by mail-pf0-f178.google.com with SMTP id 77so75537164pfv.2 for ; Mon, 09 May 2016 05:32:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2bIUNutkdMnrP4aebZebcbd3dGvseAZyxBQntfGBoXc=; b=FT58uaMiVthDV/GcwtoyE2I9EH17sVjnlj5NPM0kx8KKkJd6V3Gd12iMHeJ/rQwque w0s7bL8VaADNWISXtMsbEYHRg9bw1PhJ+n1FrAvFXEInaNofkIwswmCKapxROVuPz/8h +PacLybGCzypW7Z/scCWGYlakQW4dGOV9IN74= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2bIUNutkdMnrP4aebZebcbd3dGvseAZyxBQntfGBoXc=; b=FXo47eoX5DPy/WXnzKrKQn0sZY+vGQW9uR5mxS3Np80Eg1oCOxXYA44XLPkPKmGNrv 81sIjhhuCBKvtNtxSzfeWw5mIKJkLyHN2+iZ0aeXfiv//Ul+anBwGLuRgMfW7vLicXtp AhMBm2SoBTkinviaqy2gsV/LzoWqfXBqQYOrtj1apBFRa2FecKnrNEnXvKM/CLHJ/JP7 84fIZNu7/OYYJvfASQWTiTgNlRkrmie0eut5mo/gb8Btiw+ho10sei9yg9gNScLeyN+4 87ARx6CknwoYDXwjGUcSWAQf69ta8ez2ufobOXAdi5AbXD3QLqaxvm2bYnDNeQHoPOoW LO9w== X-Gm-Message-State: AOPr4FWSUUOlpPupfEUCc2t3zS4ebyxu6cpcjMMZj/pjAg4tgjQszMEx3ihNJOqtukINBg== X-Received: by 10.98.109.197 with SMTP id i188mr49837182pfc.88.1462797133103; Mon, 09 May 2016 05:32:13 -0700 (PDT) Received: from icarus.au.ibm.com ([2403:480:11:10:3400:b218:cbe9:48cb]) by smtp.gmail.com with ESMTPSA id i75sm17021382pfj.51.2016.05.09.05.32.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 May 2016 05:32:12 -0700 (PDT) From: Joel Stanley To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jk@ozlabs.org, benh@kernel.crashing.org, arnd@arndb.de, heiko@sntech.de Subject: [PATCH 1/4] doc/devicetree: Add Aspeed clock bindings Date: Mon, 9 May 2016 22:01:48 +0930 Message-Id: <1462797111-14271-2-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462797111-14271-1-git-send-email-joel@jms.id.au> References: <1462797111-14271-1-git-send-email-joel@jms.id.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Joel Stanley --- .../devicetree/bindings/clock/aspeed-clock.txt | 156 +++++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt diff --git a/Documentation/devicetree/bindings/clock/aspeed-clock.txt b/Documentation/devicetree/bindings/clock/aspeed-clock.txt new file mode 100644 index 000000000000..968329406435 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/aspeed-clock.txt @@ -0,0 +1,156 @@ +Device Tree Clock bindings for the Aspeed SoCs + +Aspeed SoCs have a fixed frequency input osciallator is used to create the PLL +and APB clocks. We can determine these frequencies by reading registers that +are set according to strapping bits. + +Forth generation boards +----------------------- + +eg, ast2400. + +CLKIN: + - compatible : Must be "fixed-clock" + - #clock-cells : Should be 0 + - clock-frequency: 48e6, 25e6 or 24e6 depending on the input clock + +PLL: + +Required properties: + - compatible : Must be "aspeed,g4-hpll-clock" + - #clock-cells : Should be 0 + - reg : Should contain registers location and length + - clocks : Should contain phandle + clock-specifier for the input clock (clkin) + +Optional properties: + - clock-output-names : Should contain clock name + + +APB: + +Required properties: + - compatible : Must be "aspeed,g4-apb-clock" + - #clock-cells : Should be 0 + - reg : Should contain registers location and length + - clocks : Should contain phandle + clock-specifier for the h-pll + +Optional properties: + - clock-output-names : Should contain clock name + + +For example: + + clk_clkin: clk_clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + + clk_hpll: clk_hpll { + compatible = "aspeed,g4-hpll-clock"; + #clock-cells = <0>; + reg = <0x1e6e2008 0x4>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g4-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + + +Fifth generation boards +----------------------- + +eg, ast2500. + +CLKIN: +Required properties: + - compatible : Must be "fixed-clock" + - #clock-cells : Should be 0 + - clock-frequency: 25000000 or 24000000 depending on the input clock + +H-PLL: + +Required properties: + - compatible : Must be "aspeed,g5-hpll-clock" + - #clock-cells : Should be 0 + - reg : Should contain registers location and length + - clocks : Should contain phandle + clock-specifier for the input clock (clkin) + +Optional properties: + - clock-output-names : Should contain clock name + +AHB: + +Required properties: + - compatible : Must be "aspeed,g5-ahb-clock" + - #clock-cells : Should be 0 + - reg : Should contain registers location and length + - clocks : Should contain phandle + clock-specifier for the the h-pll + +Optional properties: + - clock-output-names : Should contain clock name + +APB: + +Required properties: + - compatible : Must be "aspeed,g4-apb-clock" + - #clock-cells : Should be 0 + - reg : Should contain registers location and length + - clocks : Should contain phandle + clock-specifier for the the h-pll + +Optional properties: + - clock-output-names : Should contain clock name + +For example: + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + +Common clocks +------------- + +UART: + +All supported boards have a uart clock that is derived from a 24MHz reference. +We have a clock driver for it as there is a register in the SCU that controls +weather it will be divided down by 13 or not. + +Required properties: + - compatible : Must be "aspeed,uart-clock" + - #clock-cells : Should be 0 + - reg : Should contain registers location and length + +For example: + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + };