From patchwork Tue May 10 09:51:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 9055991 Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4C0C6BF29F for ; Tue, 10 May 2016 09:52:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 52DFA200E1 for ; Tue, 10 May 2016 09:52:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5864A200EC for ; Tue, 10 May 2016 09:52:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752061AbcEJJvx (ORCPT ); Tue, 10 May 2016 05:51:53 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:34658 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752045AbcEJJvw (ORCPT ); Tue, 10 May 2016 05:51:52 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id u4A9o2qH001762; Tue, 10 May 2016 18:50:28 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com u4A9o2qH001762 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1462873828; bh=YWTml6G57jdDTxuqC6YkbOyFXgY0xBYtsV1wcTeJTI8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0F7MZpqiNmIp9gPKPhLILj+5Qgo/q1a5TSCrDA1aLuCxwJAiIIJGObUnSEeuy7r3i ky1z6kBhsyVuUEsFvpZmUVuWH2ZLSoGckzFRSjjHl/nFNG8oxwOygD6FhPoAJTCoYA DhjDnDT6tkA61mvW7AF7YUQjQPy0nGkMeTatAZzKpwm1ikDy1nEF8gxvf8+z7JD4Xo bWc13uQVy+HR8DxYeVA4Ji9uwnXy7EkHtwZ4u5Me+ZndlhexD9M4z4bk6uDHb4bln2 CF/e5bJWFu11wqNhDsuj+vxU/ijkVpuc9hxNGrYS5aqQT2BDJiDXgefPgEScehsulO 5Kdu9PjrxxMag== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-clk@vger.kernel.org, Arnd Bergmann , Philipp Zabel Cc: Masahiro Yamada , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 20/21] reset: uniphier: add reset driver for Media I/O block on UniPhier SoCs Date: Tue, 10 May 2016 18:51:01 +0900 Message-Id: <1462873862-30940-21-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462873862-30940-1-git-send-email-yamada.masahiro@socionext.com> References: <1462873862-30940-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This series is just for review. Please do not apply this patch. Signed-off-by: Masahiro Yamada --- drivers/reset/uniphier/Kconfig | 4 ++ drivers/reset/uniphier/Makefile | 2 + drivers/reset/uniphier/reset-uniphier-mio.c | 106 ++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 drivers/reset/uniphier/reset-uniphier-mio.c diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig index 8509e71..a582938 100644 --- a/drivers/reset/uniphier/Kconfig +++ b/drivers/reset/uniphier/Kconfig @@ -34,4 +34,8 @@ config RESET_UNIPHIER_LD20 tristate "Reset driver for UniPhier PH1-LD20 SoC" default ARM64 +config RESET_UNIPHIER_MIO + tristate "Reset driver for UniPhier Media I/O block" + default y + endif diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile index a33cb0a..e83bd14 100644 --- a/drivers/reset/uniphier/Makefile +++ b/drivers/reset/uniphier/Makefile @@ -7,3 +7,5 @@ obj-$(CONFIG_RESET_UNIPHIER_PRO5) += reset-uniphier-pro5.o obj-$(CONFIG_RESET_UNIPHIER_PXS2) += reset-uniphier-pxs2.o obj-$(CONFIG_RESET_UNIPHIER_LD11) += reset-uniphier-ld11.o obj-$(CONFIG_RESET_UNIPHIER_LD20) += reset-uniphier-ld20.o + +obj-$(CONFIG_RESET_UNIPHIER_MIO) += reset-uniphier-mio.o diff --git a/drivers/reset/uniphier/reset-uniphier-mio.c b/drivers/reset/uniphier/reset-uniphier-mio.c new file mode 100644 index 0000000..f68a8cf --- /dev/null +++ b/drivers/reset/uniphier/reset-uniphier-mio.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "reset-uniphier.h" + +#define UNIPHIER_MIO_RESET_SD(ch, index) \ + { \ + .id = (index), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = BIT(26) | BIT(0), \ + .deassert_val = BIT(26) | BIT(0), \ + } + +#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(ch, index) \ + { \ + .id = (index), \ + .reg = 0x80 + 0x200 * (ch), \ + .mask = BIT(0), \ + .deassert_val = BIT(0), \ + } + +#define UNIPHIER_MIO_RESET_EHCI(ch, index) \ + { \ + .id = (index), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = BIT(24), \ + .deassert_val = BIT(24), \ + }, \ + { \ + .id = (index), \ + .reg = 0x114 + 0x200 * (ch), \ + .mask = BIT(0), \ + .deassert_val = BIT(0), \ + } + +#define UNIPHIER_MIO_RESET_DMAC(index) \ + { \ + .id = (index), \ + .reg = 0x110, \ + .mask = BIT(17), \ + .deassert_val = BIT(17), \ + } + +static const struct uniphier_reset_data uniphier_ld4_mio_reset_data[] = { + UNIPHIER_MIO_RESET_SD(0, 0), + UNIPHIER_MIO_RESET_SD(1, 1), + UNIPHIER_MIO_RESET_SD(2, 2), + UNIPHIER_MIO_RESET_DMAC(3), + UNIPHIER_MIO_RESET_EHCI(0, 4), + UNIPHIER_MIO_RESET_EHCI(1, 5), + UNIPHIER_MIO_RESET_EHCI(2, 6), + UNIPHIER_MIO_RESET_EMMC_HW_RESET(1, 9), + { .id = UNIPHIER_RESET_ID_END } +}; + +static int uniphier_ld4_mio_reset_probe(struct platform_device *pdev) +{ + return uniphier_reset_probe(pdev, uniphier_ld4_mio_reset_data); +} + +static struct platform_driver uniphier_ld4_mio_reset_driver = { + .probe = uniphier_ld4_mio_reset_probe, + .driver = { + .name = "uniphier-ld4-mio-reset", + }, +}; +module_platform_driver(uniphier_ld4_mio_reset_driver); + +static const struct uniphier_reset_data uniphier_pro5_mio_reset_data[] = { + UNIPHIER_MIO_RESET_SD(0, 0), + UNIPHIER_MIO_RESET_SD(1, 1), + UNIPHIER_MIO_RESET_EMMC_HW_RESET(1, 9), + { .id = UNIPHIER_RESET_ID_END } +}; + +static int uniphier_pro5_mio_reset_probe(struct platform_device *pdev) +{ + return uniphier_reset_probe(pdev, uniphier_pro5_mio_reset_data); +} + +static struct platform_driver uniphier_pro5_mio_reset_driver = { + .probe = uniphier_pro5_mio_reset_probe, + .driver = { + .name = "uniphier-mio-reset", + }, +}; +module_platform_driver(uniphier_pro5_mio_reset_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier Media I/O Reset Controller Driver"); +MODULE_LICENSE("GPL");