From patchwork Thu May 12 18:03:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9085351 Return-Path: X-Original-To: patchwork-linux-clk@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 47FC1BF29F for ; Thu, 12 May 2016 18:04:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5FE4620256 for ; Thu, 12 May 2016 18:04:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 734BD201FA for ; Thu, 12 May 2016 18:04:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752613AbcELSDt (ORCPT ); Thu, 12 May 2016 14:03:49 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:34741 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752443AbcELSDk (ORCPT ); Thu, 12 May 2016 14:03:40 -0400 Received: by mail-pa0-f46.google.com with SMTP id r5so32780671pag.1 for ; Thu, 12 May 2016 11:03:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JcS0vChNNbtFOJFYuZfAX2QX3neAJ2NoAgd6PH+YOwg=; b=NXWvKhFkkNxPdCT8PIuaPykouM5OF7Lh3k4JCUB7EcfAi3+kVVavo2xApmbRcYjBpd rTwAljblMr0I4a+1mR+PTd9FQro231LBjhULlhDtqLCTg0g3KSRfsIzhUGAOz0tQYKqu QHWnYfhWVrIA6pLREKN+bXqLhFXSaEF2VsvEw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JcS0vChNNbtFOJFYuZfAX2QX3neAJ2NoAgd6PH+YOwg=; b=g5685tNeVQMRFw1cZkW6J3oMoURzTjMnQmceqiDnbiULLAY2Wz9k9ZoDPjRjOv8ezm gujVRnZ7ivzCBgODuOK56XoNwZmWdfucoI72maysBe9P1N/Ehr+bRTiWsqKti0vSANza Xpg2bJo2nt9SBhVgWve6Z2AlpsD86lZjZsU32f7qEyjx+zLtiFKdg5HQSkX1q+TWyOTe I+/ic18ab+jkpzyH0piqXqrGB6Fv17EKVfwq/B7amph2rCCwv1N2n1cykRv1MDjRGBAR AKNVEXqA1c1Z+3UJyu9k3i6sefwhEWdwzcu98rqwuPCq148SCldpKlsKNYkuz4ibmf8O 5gJQ== X-Gm-Message-State: AOPr4FWSPrd9EX82whRcq0SDx/Q9Lxnbw1FJPBQT0sgV+JBeYs8TmILi1PGTedtuu+NqZQ== X-Received: by 10.66.79.197 with SMTP id l5mr15954512pax.61.1463076218880; Thu, 12 May 2016 11:03:38 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id ey12sm21422666pac.26.2016.05.12.11.03.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 May 2016 11:03:38 -0700 (PDT) From: Douglas Anderson To: Heiko Stuebner , mturquette@baylibre.com, sboyd@codeaurora.org Cc: linux-rockchip@lists.infradead.org, shawn.lin@rock-chips.com, zhengxing@rock-chips.com, Douglas Anderson , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] clk: rockchip: fix the rk3399 sdmmc sample shift Date: Thu, 12 May 2016 11:03:17 -0700 Message-Id: <1463076197-15900-2-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1463076197-15900-1-git-send-email-dianders@chromium.org> References: <1463076197-15900-1-git-send-email-dianders@chromium.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Just like every other Rockhip device, the MMC "_sample" clocks should have a shift of 0, not a shift of 1. The rk3399 TRM agrees. Presumably these values were set to 0 because of a typo. Things _sorta_ would have worked with the incorrect sample phase shift because of the register layout but wouldn't have been ideal and we would have skipped lots of phases. Also: we would never actually enabled the fine delay unless we happened to have 128 or more delay elements. This is expected behavior before this patch: * Try to set: 0 degrees + 1 delay elements Actually get: 0 degrees + 0 delay elements * Try to set: 90 degrees + 0 delay elements Actually get: 180 degrees + 0 delay elements * Try to set: 180 degrees + 0 delay elements Actually get: 0 degrees + 0 delay elements * Try to set: 270 degrees + 0 delay elements Actually get: 180 degrees + 0 delay elements * Try to set: 0 degrees + 129 delay elements Actually get: 0 degrees + 2 delay elements * Try to set: 180 degrees + 129 delay elements Actually get: 0 degrees + 3 delay elements * Try to set: 0 degrees + 130 delay elements Actually get: 0 degrees + 4 delay elements I verified that old code had a problem by turning on debug printouts and seeing that the old code would report this for one SD card I had: Good phase range 347-101 (115 len) Good phase range 202-326 (125 len) After my fix, it went down to one big good range for the same card. This is more expected: Good phase range 189-1 (173 len) Good phase range 82-85 (4 len) Good phase range 166-168 (3 len) Signed-off-by: Douglas Anderson --- drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 291543f52caa..14ff3e109e1e 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -895,10 +895,10 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKGATE_CON(6), 1, GFLAGS), MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), - MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), + MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 0), MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), - MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), + MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 0), /* pcie */ COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,