From patchwork Wed May 25 22:24:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rhyland Klein X-Patchwork-Id: 9136313 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 58A54607D3 for ; Wed, 25 May 2016 22:27:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4BD61279C4 for ; Wed, 25 May 2016 22:27:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 40E8E282F5; Wed, 25 May 2016 22:27:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B775E279C4 for ; Wed, 25 May 2016 22:27:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752156AbcEYW1Q (ORCPT ); Wed, 25 May 2016 18:27:16 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10486 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752380AbcEYWZE (ORCPT ); Wed, 25 May 2016 18:25:04 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 25 May 2016 15:25:03 -0700 Received: from HQMAIL104.nvidia.com ([172.18.146.11]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 25 May 2016 15:23:26 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 25 May 2016 15:23:26 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 25 May 2016 22:25:02 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 25 May 2016 22:25:02 +0000 Received: from rklein-work.nvidia.com (Not Verified[10.2.71.219]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 25 May 2016 15:25:02 -0700 From: Rhyland Klein To: Peter De Schrijver , Thierry Reding CC: Michael Turquette , Stephen Boyd , Alexandre Courbot , , , , Stephen Warren , Rhyland Klein Subject: [PATCH 05/11] clk: tegra30: clean up init_table Date: Wed, 25 May 2016 18:24:25 -0400 Message-ID: <1464215071-28696-6-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464215071-28696-1-git-send-email-rklein@nvidia.com> References: <1464215071-28696-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Remove entries from the init_table where the clks are now defined as CRITICAL clks, if we were only enabling them in the init_table. Remove the flag to signal to enable CRITICAL clks if they are still needed in the init_table to set other properties. Signed-off-by: Rhyland Klein --- drivers/clk/tegra/clk-tegra30.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index fc91460ab892..8ae18b63568e 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1349,12 +1349,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 }, { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 }, { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 }, - { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 }, - { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 }, - { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 }, - { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 }, - { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 }, - { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 }, + { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 }, { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, @@ -1363,11 +1359,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 }, { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 }, { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 }, - { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 }, - { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 }, - { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 }, - { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 }, - { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 }, { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 }, @@ -1378,7 +1369,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 }, - { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },