From patchwork Mon Jul 11 10:50:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9223269 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9744D60760 for ; Mon, 11 Jul 2016 10:52:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 886B0277D9 for ; Mon, 11 Jul 2016 10:52:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7D51727C38; Mon, 11 Jul 2016 10:52:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 32CC3277D9 for ; Mon, 11 Jul 2016 10:52:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758560AbcGKKvE (ORCPT ); Mon, 11 Jul 2016 06:51:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:40685 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758537AbcGKKvA (ORCPT ); Mon, 11 Jul 2016 06:51:00 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D4E0C611E1; Mon, 11 Jul 2016 10:50:59 +0000 (UTC) Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DF479600D8; Mon, 11 Jul 2016 10:50:56 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, stephen.boyd@linaro.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak Subject: [PATCH 3/6] clk: qcom: Add support to initialize alpha plls Date: Mon, 11 Jul 2016 16:20:36 +0530 Message-Id: <1468234239-28693-4-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1468234239-28693-1-git-send-email-rnayak@codeaurora.org> References: <1468234239-28693-1-git-send-email-rnayak@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a function to do initial configuration of the alpha plls Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/clk-alpha-pll.c | 23 +++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 13 +++++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index bae31f9..8b8710f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -112,6 +112,29 @@ static int wait_for_pll_offline(struct clk_alpha_pll *pll, u32 mask) #define PLL_OFFLINE_ACK BIT(28) #define PLL_ACTIVE_FLAG BIT(30) +void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + u32 val, mask; + + regmap_write(regmap, pll->offset + PLL_CONFIG_CTL, + config->config_ctl_val); + + val = config->main_output_mask; + val |= config->aux_output_mask; + val |= config->aux2_output_mask; + val |= config->early_output_mask; + val |= config->post_div_val; + + mask = config->main_output_mask; + mask |= config->aux_output_mask; + mask |= config->aux2_output_mask; + mask |= config->early_output_mask; + mask |= config->post_div_mask; + + regmap_update_bits(regmap, pll->offset + PLL_USER_CTL, mask, val); +} + static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) { int ret; diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index f78bf4c..12a349e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -51,8 +51,21 @@ struct clk_alpha_pll_postdiv { struct clk_regmap clkr; }; +struct alpha_pll_config { + u32 config_ctl_val; + u32 main_output_mask; + u32 aux_output_mask; + u32 aux2_output_mask; + u32 early_output_mask; + u32 post_div_val; + u32 post_div_mask; +}; + extern const struct clk_ops clk_alpha_pll_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ops; +void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); + #endif