From patchwork Mon Jul 18 09:41:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 9234289 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C6F186075D for ; Mon, 18 Jul 2016 09:41:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B738A20649 for ; Mon, 18 Jul 2016 09:41:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ABEE526AE3; Mon, 18 Jul 2016 09:41:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3532B20649 for ; Mon, 18 Jul 2016 09:41:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751326AbcGRJlk (ORCPT ); Mon, 18 Jul 2016 05:41:40 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:33740 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750998AbcGRJlk (ORCPT ); Mon, 18 Jul 2016 05:41:40 -0400 Received: by mail-pa0-f48.google.com with SMTP id ks6so59217214pab.0 for ; Mon, 18 Jul 2016 02:41:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=RevM/N0rwIFJV3O3GpsoYcfCHAzTZFMvaNpEnPXRfI0=; b=H6brRpPjukMIjCWF/lGASJ2fpRfaYuFagZjUzelomWmtsdyFWuv5eACxf8Cewk3SQR 2IJhIUUsCicgslcyNrqbbJfJT/GtyWfHWwg0I9g5wu/fGUIU06v74b44u3gRLBrA8WTG uwwGhuVf0js/vd6JhnYvQQ9LBXeYXFzDXKqtc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=RevM/N0rwIFJV3O3GpsoYcfCHAzTZFMvaNpEnPXRfI0=; b=faaxGgBAKFEMW2Qr+0sBIcAbgp0p3tFJqOJsV9jQMx6DcD5vdXwgBb0ZIBb4LXRsHJ hgstV7K/rUA4jk6lsby7MbAsSRBTm6pfDGNXrz3icyagte8ehMUAH0CEQcQKLTiF7Met 6S8PprmVTtTcrtK3F4uByuF+Qzn2VaCgxQelxkf+4rvYWz9ZrjUul2vi5Sjc3YAM1jgl tNHw+1R06ZmnXAQZKb/9dO6E8Gu7eaFMi7Dn5Qgq7yzamlOtTdc5Y5mAZgDYwFNHqwFk belSnGFEusL+bWZ/y8lCwyQZ2srK7TjFrG9scvP7LoHNZiW4U87wt/10wcTrJpmw/7vJ 6RQw== X-Gm-Message-State: ALyK8tJE1EkpfFGTLkrtVNbf3IxK4hhDu1ySwV1IpCFiZ7RMcl7KJ8kBOfXij1TRKF+XrasX X-Received: by 10.66.183.80 with SMTP id ek16mr55096961pac.21.1468834899367; Mon, 18 Jul 2016 02:41:39 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.9]) by smtp.gmail.com with ESMTPSA id g27sm3526771pfd.47.2016.07.18.02.41.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jul 2016 02:41:38 -0700 (PDT) From: Jun Nie To: sboyd@codeaurora.org, mturquette@baylibre.com, linux-clk@vger.kernel.org Cc: Jun Nie Subject: [PATCH 1/3] clk: zx: reform pll config info to ease code extension Date: Mon, 18 Jul 2016 17:41:15 +0800 Message-Id: <1468834877-22534-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie --- drivers/clk/zte/clk.c | 18 ++++++++++-------- drivers/clk/zte/clk.h | 2 ++ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c index 7c73c53..10d532d 100644 --- a/drivers/clk/zte/clk.c +++ b/drivers/clk/zte/clk.c @@ -21,8 +21,8 @@ #define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw) #define CFG0_CFG1_OFFSET 4 -#define LOCK_FLAG BIT(30) -#define POWER_DOWN BIT(31) +#define LOCK_FLAG 30 +#define POWER_DOWN 31 static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate) { @@ -50,8 +50,8 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll) hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); /* For matching the value in lookup table */ - hw_cfg0 &= ~LOCK_FLAG; - hw_cfg0 |= POWER_DOWN; + hw_cfg0 &= ~BIT(zx_pll->lock_bit); + hw_cfg0 |= BIT(zx_pll->pd_bit); for (i = 0; i < zx_pll->count; i++) { if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) @@ -108,10 +108,10 @@ static int zx_pll_enable(struct clk_hw *hw) u32 reg; reg = readl_relaxed(zx_pll->reg_base); - writel_relaxed(reg & ~POWER_DOWN, zx_pll->reg_base); + writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, - reg & LOCK_FLAG, 0, 100); + reg & BIT(zx_pll->lock_bit), 0, 100); } static void zx_pll_disable(struct clk_hw *hw) @@ -120,7 +120,7 @@ static void zx_pll_disable(struct clk_hw *hw) u32 reg; reg = readl_relaxed(zx_pll->reg_base); - writel_relaxed(reg | POWER_DOWN, zx_pll->reg_base); + writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); } static int zx_pll_is_enabled(struct clk_hw *hw) @@ -130,7 +130,7 @@ static int zx_pll_is_enabled(struct clk_hw *hw) reg = readl_relaxed(zx_pll->reg_base); - return !(reg & POWER_DOWN); + return !(reg & BIT(zx_pll->pd_bit)); } static const struct clk_ops zx_pll_ops = { @@ -164,6 +164,8 @@ struct clk *clk_register_zx_pll(const char *name, const char *parent_name, zx_pll->reg_base = reg_base; zx_pll->lookup_table = lookup_table; zx_pll->count = count; + zx_pll->lock_bit = LOCK_FLAG; + zx_pll->pd_bit = POWER_DOWN; zx_pll->lock = lock; zx_pll->hw.init = &init; diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h index 65ae08b..8277a0a 100644 --- a/drivers/clk/zte/clk.h +++ b/drivers/clk/zte/clk.h @@ -24,6 +24,8 @@ struct clk_zx_pll { const struct zx_pll_config *lookup_table; /* order by rate asc */ int count; spinlock_t *lock; + u8 pd_bit; /* power down bit */ + u8 lock_bit; /* pll lock flag bit */ }; struct clk *clk_register_zx_pll(const char *name, const char *parent_name,