From patchwork Sat Aug 6 19:40:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mirza Krak X-Patchwork-Id: 9266029 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C5F7160760 for ; Sat, 6 Aug 2016 20:40:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B3222283AC for ; Sat, 6 Aug 2016 20:40:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A33F828403; Sat, 6 Aug 2016 20:40:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 10D63283AC for ; Sat, 6 Aug 2016 20:40:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751529AbcHFUk3 (ORCPT ); Sat, 6 Aug 2016 16:40:29 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:35050 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750938AbcHFUk1 (ORCPT ); Sat, 6 Aug 2016 16:40:27 -0400 Received: by mail-wm0-f65.google.com with SMTP id i5so8790857wmg.2; Sat, 06 Aug 2016 13:40:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kZ3hiloJKtq5R7HEqQcixEaC6FweX9f8Izud1iT7pnA=; b=GZgTGtEu9tAfvTb+ii4A2hSRQ0hyQ0QdPKPnAMQ9FI0yzXCaAyZmGQiNRkcL5+HFxD 90ZUpEE3UhTuNJGych/AYRX2Qt9NbNULfohVraHOXaa39jaUu63BPz6DsGSpsf8aFcNV QLT/yi7x1kjteRAtdm3hCqqBWGKe/ra8RFkUKkhVHA6jLVN4TOu+WhU/Fo4rK5j+gTmx 2+VYYQe8IenqQkYPot/ZVBWRpkXSx8R5tb3pFtaiRYABEDB8cLPChBaJ7b+6BRKqP1Ar hyg2C34jxEVQrN2QDdVx4OyC6i5DtLm2qkVDnlxargGzRUYg6LpBy34wM/rXzqCjD++3 RupQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kZ3hiloJKtq5R7HEqQcixEaC6FweX9f8Izud1iT7pnA=; b=Ocd1pE0zt8l6bO1vprBjzHtAK5NrcVEUfysr5f+xOELYhEb8LrceaPhqVhP4LqsCtA 3cGxR0RwJtz2Sa4t9n+zCKZOAdN+GvJE9HwO7b3JUt46evL203F3gVk5fXfmdHWYv8bm rXPd/dDl2R4Etv/+uZ7vtLLLj4fQ76EYwfcqQiPnT4ZLrYuRq3jp2XiCidCUqqbk75Dw Yt7y5u0Hvqv9W03fd0BtSi68DtvHVnCPQp3+IFghlEnNlxEXg+tMC97jmyAiKCRXA1Lb acgUAWaP9qf6fUwfTbkBQvqBpsU3MBxcDasvoT6e39uwawodcwIxtbJc4VQzMofdW/J9 ploA== X-Gm-Message-State: AEkoouu0PTa/2ovqsJadocmDG/VyAcgTQ7B+k58+UY4HgpqTNfSo7QMJ1smeSWuN2jrlAg== X-Received: by 10.28.211.10 with SMTP id k10mr8603582wmg.16.1470512408722; Sat, 06 Aug 2016 12:40:08 -0700 (PDT) Received: from debian.lan (h39n9-klv-a11.ias.bredband.telia.com. [213.65.21.39]) by smtp.gmail.com with ESMTPSA id f3sm24332264wjh.2.2016.08.06.12.40.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 06 Aug 2016 12:40:08 -0700 (PDT) From: Mirza Krak X-Google-Original-From: Mirza Krak < mirza.krak@gmail.com > To: swarren@wwwdotorg.org, thierry.reding@gmail.com, gnurou@gmail.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@armlinux.org.uk, mturquette@baylibre.com, sboyd@codeaurora.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Mirza Krak Subject: [PATCH 6/6] bus: Add support for Tegra Generic Memory Interface Date: Sat, 6 Aug 2016 21:40:52 +0200 Message-Id: <1470512452-8322-7-git-send-email-mirza.krak@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1470512452-8322-1-git-send-email-mirza.krak@gmail.com> References: <1470512452-8322-1-git-send-email-mirza.krak@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mirza Krak The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak --- drivers/bus/Kconfig | 7 ++ drivers/bus/Makefile | 1 + drivers/bus/tegra-gmi.c | 224 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) create mode 100644 drivers/bus/tegra-gmi.c diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 3b205e2..88bbf2c 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -145,6 +145,13 @@ config TEGRA_ACONNECT Driver for the Tegra ACONNECT bus which is used to interface with the devices inside the Audio Processing Engine (APE) for Tegra210. +config TEGRA_GMI + tristate "Tegra Generic Memory Interface bus driver" + depends on ARCH_TEGRA + help + Driver for the Tegra Generic Memory Interface bus which can be used + to attach devices such as NOR, UART, FPGA and more. + config UNIPHIER_SYSTEM_BUS tristate "UniPhier System Bus driver" depends on ARCH_UNIPHIER && OF diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index ac84cc4..34e2bab 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -18,5 +18,6 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o +obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c new file mode 100644 index 0000000..7a45442 --- /dev/null +++ b/drivers/bus/tegra-gmi.c @@ -0,0 +1,224 @@ +/* + * Driver for NVIDIA Generic Memory Interface + * + * Copyright (C) 2016 Host Mobility AB. All rights reserved. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include + +#define TEGRA_GMI_CONFIG 0x00 +#define TEGRA_GMI_CONFIG_GO BIT(31) +#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30) +#define TEGRA_GMI_MUX_MODE BIT(28) +#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24) +#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23) +#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22) +#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21) +#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20) +#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4) + +#define TEGRA_GMI_TIMING0 0x10 +#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12) +#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8) +#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4) +#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf) + +#define TEGRA_GMI_TIMING1 0x14 +#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16) +#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8) +#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff) + +struct tegra_gmi_priv { + void __iomem *base; + + u32 snor_config; + u32 snor_timing0; + u32 snor_timing1; + + struct clk *clk; +}; + +static void tegra_gmi_init(struct device *dev, struct tegra_gmi_priv *priv) +{ + writel(priv->snor_timing0, priv->base + TEGRA_GMI_TIMING0); + writel(priv->snor_timing1, priv->base + TEGRA_GMI_TIMING1); + + priv->snor_config |= TEGRA_GMI_CONFIG_GO; + writel(priv->snor_config, priv->base + TEGRA_GMI_CONFIG); +} + +static int tegra_gmi_parse_dt(struct device *dev, struct tegra_gmi_priv *priv) +{ + struct device_node *of_node = dev->of_node; + u32 property; + + /* configuration */ + + if (of_property_read_bool(of_node, "nvidia,snor-data-width-32bit")) + priv->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT; + + if (of_property_read_bool(of_node, "nvidia,snor-mux-mode")) + priv->snor_config |= TEGRA_GMI_MUX_MODE; + + if (of_property_read_bool(of_node, "nvidia,snor-rdy-active-before-data")) + priv->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA; + + if (of_property_read_bool(of_node, "nvidia,snor-rdy-inv")) + priv->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH; + + if (of_property_read_bool(of_node, "nvidia,snor-adv-inv")) + priv->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH; + + if (of_property_read_bool(of_node, "nvidia,snor-oe-inv")) + priv->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH; + + if (of_property_read_bool(of_node, "nvidia,snor-cs-inv")) + priv->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH; + + if (!of_property_read_u32(of_node, "nvidia,snor-cs-select", &property)) + priv->snor_config |= TEGRA_GMI_CS_SELECT(property); + + /* Timing, the default values that are provided are reset values */ + + if (!of_property_read_u32(of_node, "nvidia,snor-muxed-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1); + + if (!of_property_read_u32(of_node, "nvidia,snor-hold-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1); + + if (!of_property_read_u32(of_node, "nvidia,snor-adv-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1); + + if (!of_property_read_u32(of_node, "nvidia,snor-ce-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4); + + if (!of_property_read_u32(of_node, "nvidia,snor-we-width", &property)) + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property); + else + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1); + + if (!of_property_read_u32(of_node, "nvidia,snor-oe-width", &property)) + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property); + else + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1); + + if (!of_property_read_u32(of_node, "nvidia,snor-wait-width", &property)) + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property); + else + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3); + + return of_platform_default_populate(of_node, NULL, dev); +} + +static int tegra_gmi_probe(struct platform_device *pdev) +{ + struct resource *res; + struct clk *clk; + struct device *dev = &pdev->dev; + struct reset_control *rst; + struct tegra_gmi_priv *priv; + void __iomem *base; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = base; + + clk = devm_clk_get(dev, "gmi"); + if (IS_ERR(clk)) { + dev_err(dev, "can not get clock\n"); + return PTR_ERR(clk); + } + + priv->clk = clk; + + rst = devm_reset_control_get(dev, "gmi"); + if (IS_ERR(rst)) { + dev_err(dev, "can not get reset\n"); + return PTR_ERR(rst); + } + + ret = tegra_gmi_parse_dt(dev, priv); + if (ret) { + dev_err(dev, "fail to create devices.\n"); + return ret; + } + + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(dev, "fail to enable clock.\n"); + return ret; + } + + reset_control_assert(rst); + udelay(2); + reset_control_deassert(rst); + + tegra_gmi_init(dev, priv); + + dev_set_drvdata(dev, priv); + + return 0; +} + +static int tegra_gmi_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tegra_gmi_priv *priv = dev_get_drvdata(dev); + void __iomem *base = priv->base; + u32 config; + + of_platform_depopulate(dev); + + config = readl(base + TEGRA_GMI_CONFIG); + config &= ~TEGRA_GMI_CONFIG_GO; + writel(config, base + TEGRA_GMI_CONFIG); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static const struct of_device_id tegra_gmi_id_table[] = { + { .compatible = "nvidia,tegra20-gmi", }, + { .compatible = "nvidia,tegra30-gmi", }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra_gmi_id_table); + +static struct platform_driver tegra_gmi_driver = { + .probe = tegra_gmi_probe, + .remove = tegra_gmi_remove, + .driver = { + .name = "tegra-gmi", + .of_match_table = tegra_gmi_id_table, + }, +}; +module_platform_driver(tegra_gmi_driver); + +MODULE_AUTHOR("Mirza Krak