From patchwork Wed Aug 10 09:09:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9274005 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0B71B600CA for ; Wed, 10 Aug 2016 20:31:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED2F627F80 for ; Wed, 10 Aug 2016 20:31:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E1CA82840C; Wed, 10 Aug 2016 20:31:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D3CF27F80 for ; Wed, 10 Aug 2016 20:31:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933467AbcHJUbv (ORCPT ); Wed, 10 Aug 2016 16:31:51 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:34872 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932295AbcHJUbt (ORCPT ); Wed, 10 Aug 2016 16:31:49 -0400 Received: by mail-wm0-f50.google.com with SMTP id f65so111465128wmi.0 for ; Wed, 10 Aug 2016 13:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Qc2eoVfwtUzV3DgWC9VJyjyJEu1HfCIJ7oKzufpagRA=; b=ZuLsOIH/RxCCVgBNB/zbzhYFiue8U7r6RucdQOwzUT+Y5S41K/LmQiB+9tkHCCWg64 9jXOE68zDJLXCOh0kg3Cc+KG8ySPq2gCWud+gd6VFfJTg/rlEhUpAlFdJZlXxrtdqvUz 1J3xQoaUw9u0AzsxNv5nnHYsAIxHt+p8NmQnw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Qc2eoVfwtUzV3DgWC9VJyjyJEu1HfCIJ7oKzufpagRA=; b=XdlhXpQJdvZFsJxQtDsUn3lxI/WCk9y4vDpnGi6Uoxwnk2P5OuV6y9aKEAdIMBGJQA 1kVmgBz43arE31EFEfgWtqciaSDf4rly30r7nBR1Qet5s3WArKlt7suvE0gllVxBEU53 B8YbE8V8cxei3/pJUmwwjLS/Zl6W5qg3/K0nj0oy1xn75agit4wBiao47r9dlZhJEkby +nsassxd+kRPbXTD6uHVW7Zu/ozfbjbyZyEKBPG6psemg8RFhg6iCFw1fuGuZ41tMxqw uETnAt1+6dkp0LVhynR5gvRKLjjlOE0DGT5MYxOLf/dA6pv4ptxh16AdJME1K1TaOJh+ nZoQ== X-Gm-Message-State: AEkoouu9WxX7a+Q4ksVa1dpAUgyCDd//gogW4N19EEobzNNJNwJ3niGwC7vlOpIwt93opuUd X-Received: by 10.25.205.200 with SMTP id d191mr461562lfg.212.1470820183566; Wed, 10 Aug 2016 02:09:43 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h22sm7417698lji.21.2016.08.10.02.09.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Aug 2016 02:09:42 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org, Russell King Subject: [PATCH 1/3] clk: versatile add DT bindings for the ICST CM variants Date: Wed, 10 Aug 2016 11:09:32 +0200 Message-Id: <1470820172-12840-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Integrator/AP and Integrator/CP core modules have special versions of the ICST525 interface hardcoding some bits. Create special compatible strings to identify these variants, also explain a bit what is going on. Cc: devicetree@vger.kernel.org Cc: Russell King Signed-off-by: Linus Walleij --- .../devicetree/bindings/clock/arm-syscon-icst.txt | 35 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt index 8b7177cecb36..48886490591a 100644 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt @@ -5,20 +5,51 @@ Technology (IDT). ARM integrated these oscillators deeply into their reference designs by adding special control registers that manage such oscillators to their system controllers. -The ARM system controller contains logic to serialize and initialize +The ARM system controllers contains logic to serialize and initialize an ICST clock request after a write to the 32 bit register at an offset into the system controller. Furthermore, to even be able to alter one of these frequencies, the system controller must first be unlocked by writing a special token to another offset in the system controller. +The ARM Integrator/AP and Integrator/CP core modules and baseboard contain +special versions of the serial interface that only connects the low 8 bits +of the VDW (missing one bit), hardwires RDW to different values and sometimes +als hardwire the output divider. They therefore have special compatible +strings as per this table (the OD value is the value on the pins, not the +resulting output divider): + +Integrator variant: RDW OD VDW + +Integrator/AP 22 1 Bit 8 0, rest variable +integratorap-cm + +Integrator/AP 46 3 Bit 8 0, rest variable +integratorap-sys + +Integrator/AP 22 or 1 17 or (33 or 25 MHz) +integratorap-pci 14 1 14 + +Integrator/CP 22 variable Bit 8 0, rest variable +integratorcp-cm-core + +Integrator/CP 22 variable Bit 8 0, rest variable +integratorcp-cm-mem + The ICST oscillator must be provided inside a system controller node. Required properties: +- compatible: must be one of + "arm,syscon-icst525" + "arm,syscon-icst307" + "arm,syscon-icst525-integratorap-cm" + "arm,syscon-icst525-integratorap-sys" + "arm,syscon-icst525-integratorap-pci" + "arm,syscon-icst525-integratorcp-cm-core" + "arm,syscon-icst525-integratorcp-cm-mem" - lock-offset: the offset address into the system controller where the unlocking register is located - vco-offset: the offset address into the system controller where the ICST control register is located (even 32 bit address) -- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307" - #clock-cells: must be <0> - clocks: parent clock, since the ICST needs a parent clock to derive its frequency from, this attribute is compulsory.