From patchwork Wed Aug 10 09:09:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9273401 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 15AEA600CA for ; Wed, 10 Aug 2016 18:23:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07477280DE for ; Wed, 10 Aug 2016 18:23:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F034528413; Wed, 10 Aug 2016 18:23:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 10B062840F for ; Wed, 10 Aug 2016 18:23:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933565AbcHJSXj (ORCPT ); Wed, 10 Aug 2016 14:23:39 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:35385 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933704AbcHJSXg (ORCPT ); Wed, 10 Aug 2016 14:23:36 -0400 Received: by mail-wm0-f47.google.com with SMTP id f65so105838838wmi.0 for ; Wed, 10 Aug 2016 11:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=D5Dxbtd1zt7qErXVo0LCcpJZWX/xg7oZCrorAZXf2Ws=; b=HUJHwaDOQ0fS9o8LoGDFdjT2zQJaHAzMNproGG75df3EWH7Wxy+MMHCd7vZhVHeTEM 5/8VbGRCjupM7V4wd1qx/znGXOY8bTZpIRP9pgMYbUEl65NXbq07Jt+JC6ch2+6ODbVz RpUSmknGbp7rfn0vuFcjQjoiO1J2hPUiAEAK4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=D5Dxbtd1zt7qErXVo0LCcpJZWX/xg7oZCrorAZXf2Ws=; b=ljkOkdKegkcJySLvFjqAvTF0zrsPXZlu1hPZvFi+M3O4BoZzYyLTRRVxwUjuC8RJsj j8P7WtOGXhF6BnR2VJsETKCU2Tn+zvQxXId75kZeWjPZ8cd8+w/F6EaBAyovDQV2I4sN CzLqGDR3EcfvdAkbQz3pAHP+3c5+6aYkwvvL0qjU+Sthbv7yyEZkuaWwVAS9Hf9GbKnY FvxNg6r9F5sp8yOpidOW+pbz83OHaN/Q4On8hXYh4WqUgC/QO2nwcQK/ulcLpaxU1UB4 6Mn+dygtBOp8TYxrBcFaof3/eYLzrdNrGzijc9S6+dQ9AGob0sh4LLOtlOJwodViuU4D Rspg== X-Gm-Message-State: AEkoouvc0SoNumT86r9rNZy91XDgX7DWi+8SeUabECpgnYKJE9lK5ZwLVEYsFIgb1IpRtf8B X-Received: by 10.25.214.166 with SMTP id p38mr444225lfi.168.1470820200843; Wed, 10 Aug 2016 02:10:00 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id g40sm7371921ljg.22.2016.08.10.02.09.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Aug 2016 02:10:00 -0700 (PDT) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij , Russell King Subject: [PATCH 3/3] clk: versatile/icst: support for AP baseboard clocks Date: Wed, 10 Aug 2016 11:09:56 +0200 Message-Id: <1470820196-12935-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds support for the two ICST525-based clocks on the Integrator/AP baseboard, as documented in the board manual "Integrator/AP ASIC Development Motherboard", ARM DUI0098 B, pages 3-15 thru 3-18. Cc: Russell King Signed-off-by: Linus Walleij --- arch/arm/boot/dts/integratorap.dts | 22 ++++++ drivers/clk/versatile/clk-icst.c | 137 +++++++++++++++++++++++++++++++++++++ 2 files changed, 159 insertions(+) diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index cf06e32ee108..16266722ce7c 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -39,6 +39,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <14745600>; + clocks = <&xtal24mhz>; }; syscon { @@ -47,6 +48,27 @@ interrupt-parent = <&pic>; /* These are the logical module IRQs */ interrupts = <9>, <10>, <11>, <12>; + + /* + * SYSCLK clocks PCIv3 bridge, system controller and the + * logic modules. + */ + sysclk: apsys@24M { + compatible = "arm,syscon-icst525-integratorap-sys"; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; + + /* One-bit control for the PCI bus clock (33 or 25 MHz) */ + pciclk: pciclk@24M { + compatible = "arm,syscon-icst525-integratorap-pci"; + #clock-cells = <0>; + lock-offset = <0x1c>; + vco-offset = <0x04>; + clocks = <&xtal24mhz>; + }; }; timer0: timer@13000000 { diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index 078ac01c379f..c44f22f52738 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -29,15 +29,20 @@ #define VERSATILE_AUX_OSC_BITS 0x7FFFF #define INTEGRATOR_AP_CM_BITS 0xFF +#define INTEGRATOR_AP_SYS_BITS 0xFF #define INTEGRATOR_CP_CM_CORE_BITS 0x7FF #define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000 +#define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8) + /** * enum icst_control_type - the type of ICST control register */ enum icst_control_type { ICST_VERSATILE, /* The standard type, all control bits available */ ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */ + ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */ + ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */ ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */ ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */ }; @@ -93,6 +98,38 @@ static int vco_get(struct clk_icst *icst, struct icst_vco *vco) } /* + * The Integrator/AP system clock on the base board can only + * access the low eight bits of the v PLL divider. Bit 8 is tied low + * and always zero, r is hardwired to 46, and the output divider is + * hardwired to 3 (divide by 4) according to the document + * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B, + * page 3-16. + */ + if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { + vco->v = val & INTEGRATOR_AP_SYS_BITS; + vco->r = 46; + vco->s = 3; + return 0; + } + + /* + * The Integrator/AP PCI clock is using an odd pattern to create + * the child clock, basically a single bit called DIVX/Y is used + * to select between two different hardwired values: setting the + * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the + * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies + * 33 or 25 MHz respectively. + */ + if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { + bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ); + + vco->v = divxy ? 17 : 14; + vco->r = divxy ? 22 : 14; + vco->s = 1; + return 0; + } + + /* * The Integrator/CP core clock can access the low eight bits * of the v PLL divider. Bit 8 is tied low and always zero, * r is hardwired to 22 and the output divider s is accessible @@ -143,6 +180,17 @@ static int vco_set(struct clk_icst *icst, struct icst_vco vco) if (vco.r != 22) pr_err("ICST error: tried to use RDW != 22\n"); break; + case ICST_INTEGRATOR_AP_SYS: + mask = INTEGRATOR_AP_SYS_BITS; + val &= ~0xFF; /* Uses 8 bits */ + val |= vco.v & 0xFF; + if (vco.v & 0x100) + pr_err("ICST error: tried to set bit 8 of VDW\n"); + if (vco.s != 3) + pr_err("ICST error: tried to use VOD != 1\n"); + if (vco.r != 46) + pr_err("ICST error: tried to use RDW != 22\n"); + break; case ICST_INTEGRATOR_CP_CM_CORE: mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */ val = (vco.v & 0xFF) | vco.s << 8; @@ -225,6 +273,27 @@ static long icst_round_rate(struct clk_hw *hw, unsigned long rate, return DIV_ROUND_CLOSEST(rate, 500000) * 500000; } + if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { + /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ + if (rate <= 3000000) + return 3000000; + if (rate >= 50000000) + return 5000000; + /* Slam to closest 0.25 MHz */ + return DIV_ROUND_CLOSEST(rate, 250000) * 250000; + } + + if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { + /* + * If we're below or less than halfway from 25 to 33 MHz + * select 25 MHz + */ + if (rate <= 25000000 || rate < 29000000) + return 25000000; + /* Else just return the default frequency */ + return 33000000; + } + vco = icst_hz_to_vco(icst->params, rate); return icst_hz(icst->params, vco); } @@ -235,6 +304,36 @@ static int icst_set_rate(struct clk_hw *hw, unsigned long rate, struct clk_icst *icst = to_icst(hw); struct icst_vco vco; + if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { + /* This clock is especially primitive */ + unsigned int val; + int ret; + + if (rate == 25000000) { + val = 0; + } else if (rate == 33000000) { + val = INTEGRATOR_AP_PCI_25_33_MHZ; + } else { + pr_err("ICST: cannot set PCI frequency %lu\n", + rate); + return -EINVAL; + } + ret = regmap_write(icst->map, icst->lockreg_off, + VERSATILE_LOCK_VAL); + if (ret) + return ret; + ret = regmap_update_bits(icst->map, icst->vcoreg_off, + INTEGRATOR_AP_PCI_25_33_MHZ, + val); + if (ret) + return ret; + /* This locks the VCO again */ + ret = regmap_write(icst->map, icst->lockreg_off, 0); + if (ret) + return ret; + return 0; + } + if (parent_rate) icst->params->ref = parent_rate; vco = icst_hz_to_vco(icst->params, rate); @@ -368,6 +467,34 @@ static const struct icst_params icst525_apcp_cm_params = { .idx2s = icst525_idx2s, }; +static const struct icst_params icst525_ap_sys_params = { + .vco_max = ICST525_VCO_MAX_5V, + .vco_min = ICST525_VCO_MIN, + /* Minimum 3 MHz, VDW = 4 */ + .vd_min = 3, + /* Maximum 50 MHz, VDW = 192 */ + .vd_max = 50, + /* r is hardcoded to 46 and this is the actual divisor, +2 */ + .rd_min = 48, + .rd_max = 48, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, +}; + +static const struct icst_params icst525_ap_pci_params = { + .vco_max = ICST525_VCO_MAX_5V, + .vco_min = ICST525_VCO_MIN, + /* Minimum 25 MHz */ + .vd_min = 25, + /* Maximum 33 MHz */ + .vd_max = 33, + /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */ + .rd_min = 16, + .rd_max = 24, + .s2div = icst525_s2div, + .idx2s = icst525_idx2s, +}; + static void __init of_syscon_icst_setup(struct device_node *np) { struct device_node *parent; @@ -408,6 +535,12 @@ static void __init of_syscon_icst_setup(struct device_node *np) } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) { icst_desc.params = &icst525_apcp_cm_params; ctype = ICST_INTEGRATOR_AP_CM; + } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) { + icst_desc.params = &icst525_ap_sys_params; + ctype = ICST_INTEGRATOR_AP_SYS; + } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) { + icst_desc.params = &icst525_ap_pci_params; + ctype = ICST_INTEGRATOR_AP_PCI; } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) { icst_desc.params = &icst525_apcp_cm_params; ctype = ICST_INTEGRATOR_CP_CM_CORE; @@ -437,6 +570,10 @@ CLK_OF_DECLARE(arm_syscon_icst307_clk, "arm,syscon-icst307", of_syscon_icst_setup); CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk, "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup); +CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk, + "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup); +CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk, + "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup); CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk, "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup); CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,