From patchwork Thu Aug 11 08:40:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9274657 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DF2BD60231 for ; Thu, 11 Aug 2016 08:44:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CCFA827FE4 for ; Thu, 11 Aug 2016 08:44:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1ECC28574; Thu, 11 Aug 2016 08:44:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1853327FE4 for ; Thu, 11 Aug 2016 08:44:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932620AbcHKImc (ORCPT ); Thu, 11 Aug 2016 04:42:32 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57598 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932486AbcHKIm2 (ORCPT ); Thu, 11 Aug 2016 04:42:28 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9525B61378; Thu, 11 Aug 2016 08:41:45 +0000 (UTC) Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6A16761370; Thu, 11 Aug 2016 08:41:42 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, tdas@codeaurora.org, Rajendra Nayak Subject: [PATCH v2 10/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update Date: Thu, 11 Aug 2016 14:10:58 +0530 Message-Id: <1470904858-11930-11-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1470904858-11930-1-git-send-email-rnayak@codeaurora.org> References: <1470904858-11930-1-git-send-email-rnayak@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Taniya Das Alpha PLLs which do not support dynamic update feature need to be explicitly disabled before a rate change. The ones which do support dynamic update don't have to be disabled but need to follow a update sequence (as implemented by clk_alpha_pll_dynamic_update() in the patch). They also need the PLL_HW_LOGIC_BYPASS bit set at init. Signed-off-by: Taniya Das Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/clk-alpha-pll.c | 48 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 49 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 2184dc1..68c90f3 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -113,6 +113,11 @@ static int wait_for_pll_offline(struct clk_alpha_pll *pll, u32 mask) #define PLL_OFFLINE_ACK BIT(28) #define PLL_ACTIVE_FLAG BIT(30) +/* alpha pll with dynamic update support */ +#define PLL_UPDATE BIT(22) +#define PLL_HW_LOGIC_BYPASS BIT(23) +#define PLL_ACK_LATCH BIT(29) + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { @@ -138,6 +143,37 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, if (pll->flags & SUPPORTS_VOTE_FSM) qcom_pll_set_fsm_mode(regmap, pll->offset + PLL_MODE, 6, 0); + if (pll->flags & SUPPORTS_DYNAMIC_UPDATE) + regmap_update_bits(regmap, pll->offset + PLL_MODE, + PLL_HW_LOGIC_BYPASS, + PLL_HW_LOGIC_BYPASS); +} + +static int clk_alpha_pll_dynamic_update(struct clk_alpha_pll *pll) +{ + u32 val; + + /* Latch the input to the PLL */ + regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, + PLL_UPDATE, PLL_UPDATE); + + /* Wait for 2 reference cycle before checking ACK bit */ + udelay(1); + + regmap_read(pll->clkr.regmap, pll->offset + PLL_MODE, &val); + if (!(val & PLL_ACK_LATCH)) { + WARN(1, "PLL latch failed. Output may be unstable!\n"); + return -EINVAL; + } + + /* Return latch input to 0 */ + regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE, + PLL_UPDATE, 0); + + /* Wait for PLL output to stabilize */ + udelay(100); + + return 0; } static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) @@ -366,6 +402,7 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { + int enabled; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); const struct pll_vco *vco; u32 l, off = pll->offset; @@ -378,6 +415,11 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; } + enabled = hw->init->ops->is_enabled(hw); + + if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled) + hw->init->ops->disable(hw); + a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); @@ -391,6 +433,12 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN, PLL_ALPHA_EN); + if (!(pll->flags & SUPPORTS_DYNAMIC_UPDATE) && enabled) + hw->init->ops->enable(hw); + + if (pll->flags & SUPPORTS_DYNAMIC_UPDATE) + clk_alpha_pll_dynamic_update(pll); + return 0; } diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 4bd42fd..23e32db 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -36,6 +36,7 @@ struct clk_alpha_pll { size_t num_vco; #define SUPPORTS_VOTE_FSM BIT(0) +#define SUPPORTS_DYNAMIC_UPDATE BIT(1) u8 flags; struct clk_regmap clkr; };