From patchwork Tue Sep 6 06:02:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 9315741 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E326360752 for ; Tue, 6 Sep 2016 06:03:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E5A77287B8 for ; Tue, 6 Sep 2016 06:03:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DA6CF288F0; Tue, 6 Sep 2016 06:03:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 79A47287B8 for ; Tue, 6 Sep 2016 06:03:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752911AbcIFGDL (ORCPT ); Tue, 6 Sep 2016 02:03:11 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:35920 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754616AbcIFGDK (ORCPT ); Tue, 6 Sep 2016 02:03:10 -0400 Received: by mail-pa0-f48.google.com with SMTP id id6so9402200pad.3 for ; Mon, 05 Sep 2016 23:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8wn0qEq3i2Xalz8YLkYC1A7vfh+BmezbvDCQGmD9a3I=; b=O9pOVZB5XYWMNRsr8XJOm299HtPIa4u/ohj9sHbQrNa+vqyVEup9O2tioBrbvKcm/i 5ewABwUEZgUI3fe5ezMkQ0vHUYG2p2eCOzrXk/mwxKbGS1nPcE+UPli/OYbCLOI9xWlc k5wsEDoWv21F2YxTEiJysStov4RcVufCGJNVM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8wn0qEq3i2Xalz8YLkYC1A7vfh+BmezbvDCQGmD9a3I=; b=iJJoUn4GHNIbnbzYglKEkJ3bcj/vHblev1zXRDJ5PdMIcolEinWDbc7jJPenZ7VR1R XnKPxaELMY/VGfbiO41MNtFpmKfMq2jh++jdRwI0lQxYPKuIMVatSHNVfKDBbL7Iu8Vm ibekj5goHBOJKEawHQUCqDKZjFsB+lr9UeY2SMXzxDty8mVZp7Nj7/1L1O1ZIAfHEMUl 0SMfiFg5j2jyX/1uXCY2l+yoQnWioqb0vTKFNDrpItPO50FOH+GrMLZi5/R2qxzzMG4g Qja06F8/W27PTP8xLZWvZNTDlgURS7yRobvraIhkC/wQhie7lbDQtWf3kw6u5dQAAaLo iGhg== X-Gm-Message-State: AE9vXwP2IfswBkEqS1Zxb/4+PrSRcZ0pjaslQz52XgNVDsBh8mLTd08+GaiL70yjcjhE2h+n X-Received: by 10.66.43.164 with SMTP id x4mr68937447pal.11.1473141789598; Mon, 05 Sep 2016 23:03:09 -0700 (PDT) Received: from localhost.localdomain ([113.29.230.77]) by smtp.gmail.com with ESMTPSA id d5sm37491000pfc.4.2016.09.05.23.03.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Sep 2016 23:03:09 -0700 (PDT) From: Jun Nie To: mturquette@baylibre.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org Cc: shawn.guo@linaro.org, jason.liu@linaro.org, Jun Nie Subject: [PATCH v3 1/2] clk: zx: reform pll config info to ease code extension Date: Tue, 6 Sep 2016 14:02:41 +0800 Message-Id: <1473141762-4775-2-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1473141762-4775-1-git-send-email-jun.nie@linaro.org> References: <1473141762-4775-1-git-send-email-jun.nie@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie --- drivers/clk/zte/clk.c | 21 ++++++++++++--------- drivers/clk/zte/clk.h | 4 ++++ 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c index 7c73c53..c4c1251 100644 --- a/drivers/clk/zte/clk.c +++ b/drivers/clk/zte/clk.c @@ -21,8 +21,8 @@ #define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw) #define CFG0_CFG1_OFFSET 4 -#define LOCK_FLAG BIT(30) -#define POWER_DOWN BIT(31) +#define LOCK_FLAG 30 +#define POWER_DOWN 31 static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate) { @@ -50,8 +50,8 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll) hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); /* For matching the value in lookup table */ - hw_cfg0 &= ~LOCK_FLAG; - hw_cfg0 |= POWER_DOWN; + hw_cfg0 &= ~BIT(zx_pll->lock_bit); + hw_cfg0 |= BIT(zx_pll->pd_bit); for (i = 0; i < zx_pll->count; i++) { if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) @@ -108,10 +108,10 @@ static int zx_pll_enable(struct clk_hw *hw) u32 reg; reg = readl_relaxed(zx_pll->reg_base); - writel_relaxed(reg & ~POWER_DOWN, zx_pll->reg_base); + writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, - reg & LOCK_FLAG, 0, 100); + reg & BIT(zx_pll->lock_bit), 0, 100); } static void zx_pll_disable(struct clk_hw *hw) @@ -120,7 +120,7 @@ static void zx_pll_disable(struct clk_hw *hw) u32 reg; reg = readl_relaxed(zx_pll->reg_base); - writel_relaxed(reg | POWER_DOWN, zx_pll->reg_base); + writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); } static int zx_pll_is_enabled(struct clk_hw *hw) @@ -130,10 +130,10 @@ static int zx_pll_is_enabled(struct clk_hw *hw) reg = readl_relaxed(zx_pll->reg_base); - return !(reg & POWER_DOWN); + return !(reg & BIT(zx_pll->pd_bit)); } -static const struct clk_ops zx_pll_ops = { +const struct clk_ops zx_pll_ops = { .recalc_rate = zx_pll_recalc_rate, .round_rate = zx_pll_round_rate, .set_rate = zx_pll_set_rate, @@ -141,6 +141,7 @@ static const struct clk_ops zx_pll_ops = { .disable = zx_pll_disable, .is_enabled = zx_pll_is_enabled, }; +EXPORT_SYMBOL(zx_pll_ops); struct clk *clk_register_zx_pll(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg_base, @@ -164,6 +165,8 @@ struct clk *clk_register_zx_pll(const char *name, const char *parent_name, zx_pll->reg_base = reg_base; zx_pll->lookup_table = lookup_table; zx_pll->count = count; + zx_pll->lock_bit = LOCK_FLAG; + zx_pll->pd_bit = POWER_DOWN; zx_pll->lock = lock; zx_pll->hw.init = &init; diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h index 65ae08b..8f6b5f0 100644 --- a/drivers/clk/zte/clk.h +++ b/drivers/clk/zte/clk.h @@ -24,6 +24,8 @@ struct clk_zx_pll { const struct zx_pll_config *lookup_table; /* order by rate asc */ int count; spinlock_t *lock; + u8 pd_bit; /* power down bit */ + u8 lock_bit; /* pll lock flag bit */ }; struct clk *clk_register_zx_pll(const char *name, const char *parent_name, @@ -38,4 +40,6 @@ struct clk_zx_audio { struct clk *clk_register_zx_audio(const char *name, const char * const parent_name, unsigned long flags, void __iomem *reg_base); + +extern const struct clk_ops zx_pll_ops; #endif