From patchwork Thu Oct 27 14:01:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mirza Krak X-Patchwork-Id: 9399483 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3D74760588 for ; Thu, 27 Oct 2016 14:18:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F0362A2FB for ; Thu, 27 Oct 2016 14:18:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 11F642A313; Thu, 27 Oct 2016 14:18:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B51F2A2FB for ; Thu, 27 Oct 2016 14:18:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030373AbcJ0OPm (ORCPT ); Thu, 27 Oct 2016 10:15:42 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:35582 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935834AbcJ0OBZ (ORCPT ); Thu, 27 Oct 2016 10:01:25 -0400 Received: by mail-lf0-f65.google.com with SMTP id x79so2023923lff.2; Thu, 27 Oct 2016 07:01:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k9UGbYx0A3s7MPpZoEEcM+E1vUmVcXVUUHfqrITqijQ=; b=AVrbGtT/yZqjkfDH6En37d9DIWW3b9QlTjSlBjH3v4UfB7TST5ZQcbDjo1gPTolPNK 151D76RVB6hr7RoTRc6oWx9bByBUmN6cavoyCaUnCt8emArxw8oR5LfJmUX72Po8qUW7 6LWs5e2S+UpzRyNqpcW6k/dXmhrGQkWa0eEl47LnsT8sA3tX4woq5N1L5jeRQqBvEnmb 2TEWDVYmetjD/Ttj1Nq0oqGf0bOXljvsYUh9vmHF2Jc61o7yOnj2Am4ZOZ+nR+P0i0xt oHOKdFkgV+3cGxkVpDnAkTPAmw9gtLMCvStZPuvV67HvPIGDLLvMvY8QcZv1ry0LcslM GrPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k9UGbYx0A3s7MPpZoEEcM+E1vUmVcXVUUHfqrITqijQ=; b=mLm/o9kT3ndZP+NQj53vDUkna8lQdK8xjRk5hMjdl2owwfnFsfaxmvhvXoVWg3Y0IO G3vHMbfkyB1XGeF1qq3KD581xxmLt33eLEHXAqju3119O4K6FsJ8WJBjxsXx15nhG9fB RLxFUz3Lguje084GZKeUeRO+ySqBrngydJYl5h0nNGc4nSU3D2yoGB+o/gAM6A6aA7rq q8bBvph2YH6DbBIC2nh2MKjPSq4BhFlyQB+Ba1TZQC31BvG12XMdkiQjWRvOUUVuB/ta gJdPlzSZNc7Tyc+yGGIHtVtpjY7uZbrEUv75vThTaiWJuqD3UFLTQyR/xd/6atljPASa 3l1A== X-Gm-Message-State: ABUngvdNpFgh3K4ZGrCTXZrljW7owLnBX/xbXCBooSZ4bOMX8LiHsyrGent3JsUsjxiUDw== X-Received: by 10.25.21.12 with SMTP id l12mr5587035lfi.152.1477576882293; Thu, 27 Oct 2016 07:01:22 -0700 (PDT) Received: from mirza-hm.lan ([80.252.212.150]) by smtp.gmail.com with ESMTPSA id 187sm1302752ljj.4.2016.10.27.07.01.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 27 Oct 2016 07:01:21 -0700 (PDT) From: Mirza Krak X-Google-Original-From: Mirza Krak < mirza.krak@gmail.com > To: swarren@wwwdotorg.org, thierry.reding@gmail.com, jonathanh@nvidia.com Cc: gnurou@gmail.com, linux@armlinux.org.uk, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Mirza Krak Subject: [PATCH V3 3/6] dt/bindings: Add bindings for Tegra GMI controller Date: Thu, 27 Oct 2016 16:01:09 +0200 Message-Id: <1477576872-2665-4-git-send-email-mirza.krak@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1477576872-2665-1-git-send-email-mirza.krak@gmail.com> References: <1477576872-2665-1-git-send-email-mirza.krak@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mirza Krak Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Rob Herring --- Changes in v2: - Updated examples and some information based on comments from Jon Hunter. Changes in v3: - Updates ranges description based on comments from Rob Herring .../devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 132 +++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt new file mode 100644 index 0000000..49bda2f --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt @@ -0,0 +1,132 @@ +Device tree bindings for NVIDIA Tegra Generic Memory Interface bus + +The Generic Memory Interface bus enables memory transfers between internal and +external memory. Can be used to attach various high speed devices such as +synchronous/asynchronous NOR, FPGA, UARTS and more. + +The actual devices are instantiated from the child nodes of a GMI node. + +Required properties: + - compatible : Should contain one of the following: + For Tegra20 must contain "nvidia,tegra20-gmi". + For Tegra30 must contain "nvidia,tegra30-gmi". + - reg: Should contain GMI controller registers location and length. + - clocks: Must contain an entry for each entry in clock-names. + - clock-names: Must include the following entries: "gmi" + - resets : Must contain an entry for each entry in reset-names. + - reset-names : Must include the following entries: "gmi" + - #address-cells: The number of cells used to represent physical base + addresses in the GMI address space. Should be 2. + - #size-cells: The number of cells used to represent the size of an address + range in the GMI address space. Should be 1. + - ranges: Must be set up to reflect the memory layout with three integer values + for each chip-select line in use (only one entry is supported, see below + comments): + + +Note that the GMI controller does not have any internal chip-select address +decoding, because of that chip-selects either need to be managed via software +or by employing external chip-select decoding logic. + +If external chip-select logic is used to support multiple devices it is assumed +that the devices use the same timing and so are probably the same type. It also +assumes that they can fit in the 256MB address range. In this case only one +child device is supported which represents the active chip-select line, see +examples for more insight. + +The chip-select number is decoded from the child nodes second address cell of +'ranges' property, if 'ranges' property is not present or empty chip-select will +then be decoded from the first cell of the 'reg' property. + +Optional child cs node properties: + + - nvidia,snor-data-width-32bit: Use 32bit data-bus, default is 16bit. + - nvidia,snor-mux-mode: Enable address/data MUX mode. + - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data. + If omitted it will be asserted with data. + - nvidia,snor-rdy-inv: RDY signal is active high + - nvidia,snor-adv-inv: ADV signal is active high + - nvidia,snor-oe-inv: WE/OE signal is active high + - nvidia,snor-cs-inv: CS signal is active high + + Note that there is some special handling for the timing values. + From Tegra TRM: + Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1 + + - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the + bus. Valid values are 0-15, default is 1 + - nvidia,snor-hold-width: Number of cycles CE stays asserted after the + de-assertion of WR_N (in case of SLAVE/MASTER Request) or OE_N + (in case of MASTER Request). Valid values are 0-15, default is 1 + - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted. + Valid values are 0-15, default is 1. + - nvidia,snor-ce-width: Number of cycles before CE is asserted. + Valid values are 0-15, default is 4 + - nvidia,snor-we-width: Number of cycles during which WE stays asserted. + Valid values are 0-15, default is 1 + - nvidia,snor-oe-width: Number of cycles during which OE stays asserted. + Valid values are 0-255, default is 1 + - nvidia,snor-wait-width: Number of cycles before READY is asserted. + Valid values are 0-255, default is 3 + +Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the +controllers with a simple-bus node since they are all connected to the same +chip-select (CS4), in this example external address decoding is provided: + +gmi@70090000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + ranges = <4 0 0xd0000000 0xfffffff>; + + status = "okay"; + + bus@4,0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 4 0 0x40100>; + + nvidia,snor-mux-mode; + nvidia,snor-adv-inv; + + can@0 { + reg = <0 0x100>; + ... + }; + + can@40000 { + reg = <0x40000 0x100>; + ... + }; + }; +}; + +Example with one SJA1000 CAN controller connected to the GMI bus +on CS4: + +gmi@70090000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + ranges = <4 0 0xd0000000 0xfffffff>; + + status = "okay"; + + can@4,0 { + reg = <4 0 0x100>; + nvidia,snor-mux-mode; + nvidia,snor-adv-inv; + ... + }; +};