From patchwork Mon Feb 6 12:15:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mars Cheng X-Patchwork-Id: 9557677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D3D7B60242 for ; Mon, 6 Feb 2017 12:19:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4F4E2808F for ; Mon, 6 Feb 2017 12:19:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B53DB2810E; Mon, 6 Feb 2017 12:19:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5972E2808F for ; Mon, 6 Feb 2017 12:19:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751960AbdBFMQM (ORCPT ); Mon, 6 Feb 2017 07:16:12 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:15695 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751588AbdBFMQK (ORCPT ); Mon, 6 Feb 2017 07:16:10 -0500 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2038168291; Mon, 06 Feb 2017 20:16:05 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Mon, 6 Feb 2017 20:16:03 +0800 From: Mars Cheng To: Matthias Brugger CC: CC Hwang , Loda Chou , Miles Chen , Jades Shih , Yingjoe Chen , My Chuang , , , , , Marc Zyngier , Thomas Gleixner , Will Deacon , Stephen Boyd , , Chieh-Jay Liu , Mars Cheng Subject: [PATCH v2 01/10] Document: DT: mediatek: multiple base address support for sysirq Date: Mon, 6 Feb 2017 20:15:27 +0800 Message-ID: <1486383336-16892-2-git-send-email-mars.cheng@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1486383336-16892-1-git-send-email-mars.cheng@mediatek.com> References: <1486383336-16892-1-git-send-email-mars.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This describes how to specify multiple base addresses for sysirq in mediatek platforms. Signed-off-by: Mars Cheng --- .../interrupt-controller/mediatek,sysirq.txt | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 9d1d72c..1718454 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -18,16 +18,21 @@ Required properties: "mediatek,mt2701-sysirq" - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. +- #intpol-bases: Indicate how many base addresses to be used, default is 1. - interrupt-parent: phandle of irq parent for sysirq. The parent must use the same interrupt-cells format as GIC. - reg: Physical base address of the intpol registers and length of memory - mapped region. + mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others + need 1. If not set, the default is 1. Example: - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6797-sysirq", + "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; + #intpol-bases = <2>; interrupt-parent = <&gic>; - reg = <0 0x10200100 0 0x1c>; + reg = <0 0x10220620 0 0x20>, + <0 0x10220690 0 0x10>; };