From patchwork Thu Mar 2 14:16:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 9600933 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 887A860429 for ; Thu, 2 Mar 2017 16:49:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7BA7828112 for ; Thu, 2 Mar 2017 16:49:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 702C02858D; Thu, 2 Mar 2017 16:49:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA6C228112 for ; Thu, 2 Mar 2017 16:49:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754076AbdCBQsd (ORCPT ); Thu, 2 Mar 2017 11:48:33 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19280 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753904AbdCBQsW (ORCPT ); Thu, 2 Mar 2017 11:48:22 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 02 Mar 2017 06:16:30 -0800 Received: from HQMAIL106.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 02 Mar 2017 06:16:27 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 02 Mar 2017 06:16:27 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Thu, 2 Mar 2017 14:16:27 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Thu, 2 Mar 2017 14:16:23 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id ED779F8005C; Thu, 2 Mar 2017 16:16:18 +0200 (EET) From: Peter De Schrijver To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , "Stephen Boyd" , Stephen Warren , "Thierry Reding" , Alexandre Courbot , , , CC: Mikko Perttunen Subject: [PATCH] clk: tegra: Implement reset control reset Date: Thu, 2 Mar 2017 16:16:16 +0200 Message-ID: <1488464177-24174-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mikko Perttunen For completeness, also implement this reset framework API for Tegra. Signed-off-by: Mikko Perttunen Reviewed-by: Peter De Schrijver Reviewed-by: Arto Merilainen --- drivers/clk/tegra/clk.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index b2cdd9a..ba923f0 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,20 @@ static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev, return -EINVAL; } +static int tegra_clk_rst_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int err; + + err = tegra_clk_rst_assert(rcdev, id); + if (err) + return err; + + udelay(1); + + return tegra_clk_rst_deassert(rcdev, id); +} + const struct tegra_clk_periph_regs *get_reg_bank(int clkid) { int reg_bank = clkid / 32; @@ -274,6 +289,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, static const struct reset_control_ops rst_ops = { .assert = tegra_clk_rst_assert, .deassert = tegra_clk_rst_deassert, + .reset = tegra_clk_rst_reset, }; static struct reset_controller_dev rst_ctlr = {