| Message ID | 1489421994-19707-2-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
Hi Geert > The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which > maps to S3D1 or R-Car H3 ES1.x. > All module clocks must be sorted by clock ID. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > --- If my English skill was OK, - maps to S3D1 or R-Car H3 ES1.x. + maps to S3D1 on R-Car H3 ES1.x. except it Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c > index 2add8218e0f7a6c0..cde470ce81e449cf 100644 > --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c > @@ -142,8 +142,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { > DEF_MOD("rwdt0", 402, R8A7795_CLK_R), > DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), > DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), > - DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), > - DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), > + DEF_MOD("audmac1", 501, R8A7795_CLK_S3D1), > + DEF_MOD("audmac0", 502, R8A7795_CLK_S3D1), > DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), > DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), > DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), > -- > 2.7.4 > -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 2add8218e0f7a6c0..cde470ce81e449cf 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -142,8 +142,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("rwdt0", 402, R8A7795_CLK_R), DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), - DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), - DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), + DEF_MOD("audmac1", 501, R8A7795_CLK_S3D1), + DEF_MOD("audmac0", 502, R8A7795_CLK_S3D1), DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which maps to S3D1 or R-Car H3 ES1.x. All module clocks must be sorted by clock ID. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)