From patchwork Tue Mar 21 08:38:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 9636225 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1C1836020B for ; Tue, 21 Mar 2017 08:39:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 193C527CF3 for ; Tue, 21 Mar 2017 08:39:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0E07327F10; Tue, 21 Mar 2017 08:39:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B046827CF3 for ; Tue, 21 Mar 2017 08:39:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756741AbdCUIjo (ORCPT ); Tue, 21 Mar 2017 04:39:44 -0400 Received: from mail.kernel.org ([198.145.29.136]:45102 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753601AbdCUIjn (ORCPT ); Tue, 21 Mar 2017 04:39:43 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8D8FE2035D; Tue, 21 Mar 2017 08:39:36 +0000 (UTC) Received: from localhost.localdomain (li411-102.members.linode.com [106.187.91.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1E2CC20392; Tue, 21 Mar 2017 08:39:10 +0000 (UTC) From: Shawn Guo To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jun Nie , Baoyou Xie , Xin Zhou , Shawn Guo Subject: [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks Date: Tue, 21 Mar 2017 16:38:21 +0800 Message-Id: <1490085503-15713-2-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490085503-15713-1-git-send-email-shawnguo@kernel.org> References: <1490085503-15713-1-git-send-email-shawnguo@kernel.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shawn Guo To support VOU VGA display driver with different modes, we need to set flag for a few clocks, so that clk_set_rate() call in VOU driver can get VGA device desired pixel rate. While at it, the divider between pll_vga and clk_vga gets corrected, as it's 1:1 instead of 1:2. Signed-off-by: Shawn Guo Reviewed-by: Jun Nie --- drivers/clk/zte/clk-zx296718.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c index 2f7c668643fe..f2e1e8b3a8d5 100644 --- a/drivers/clk/zte/clk-zx296718.c +++ b/drivers/clk/zte/clk-zx296718.c @@ -409,7 +409,7 @@ FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0), /* vga */ FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0), - FFACTOR(0, "clk_vga", "pll_vga", 1, 2, 0), + FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT), /* pll ddr */ FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0), @@ -458,8 +458,8 @@ MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2), MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3), MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3), - MUX(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3), - MUX(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3), + MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0), + MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0), MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3), MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1), MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3),