From patchwork Tue Mar 21 13:43:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 9636625 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0A5A460216 for ; Tue, 21 Mar 2017 13:43:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 035E627C0B for ; Tue, 21 Mar 2017 13:43:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E8DC127D29; Tue, 21 Mar 2017 13:43:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 68C6827C0B for ; Tue, 21 Mar 2017 13:43:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757076AbdCUNnf (ORCPT ); Tue, 21 Mar 2017 09:43:35 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12086 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756497AbdCUNne (ORCPT ); Tue, 21 Mar 2017 09:43:34 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 21 Mar 2017 06:43:03 -0700 Received: from HQMAIL104.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 21 Mar 2017 06:43:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 21 Mar 2017 06:43:33 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 21 Mar 2017 13:43:32 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 21 Mar 2017 13:43:29 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 8AF70F8005C; Tue, 21 Mar 2017 15:43:28 +0200 (EET) From: Peter De Schrijver To: Peter De Schrijver , Michael Turquette , Stephen Boyd , , Subject: [PATCH] clk: Re-evaluate clock rate on min/max update Date: Tue, 21 Mar 2017 15:43:26 +0200 Message-ID: <1490103807-21821-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Whenever a user change its min or max rate limit of a clock, we need to re-evaluate the current clock rate and possibly change it if the new limits require so. To do this clk_set_rate_range() already calls clk_core_set_rate_nolock, however this won't have the intended effect because the core clock rate hasn't changed. To fix this, move the test to avoid setting the same core clock rate again, to clk_set_rate() so clk_core_set_rate_nolock() can change the clock rate when min or max have been updated, even when the core clock rate has not changed. Signed-off-by: Peter De Schrijver --- drivers/clk/clk.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 2fa2fb8..0b815d1 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1569,10 +1569,6 @@ static int clk_core_set_rate_nolock(struct clk_core *core, if (!core) return 0; - /* bail early if nothing to do */ - if (rate == clk_core_get_rate_nolock(core)) - return 0; - if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count) return -EBUSY; @@ -1621,16 +1617,21 @@ static int clk_core_set_rate_nolock(struct clk_core *core, */ int clk_set_rate(struct clk *clk, unsigned long rate) { - int ret; + int ret = 0; if (!clk) - return 0; + return ret; /* prevent racing with updates to the clock topology */ clk_prepare_lock(); + /* bail early if nothing to do */ + if (rate == clk_core_get_rate_nolock(clk->core)) + goto out; + ret = clk_core_set_rate_nolock(clk->core, rate); +out: clk_prepare_unlock(); return ret;