From patchwork Wed Apr 5 04:55:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 9662933 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4970960364 for ; Wed, 5 Apr 2017 04:56:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A0B328494 for ; Wed, 5 Apr 2017 04:56:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2EE09284CE; Wed, 5 Apr 2017 04:56:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D0FA3284CC for ; Wed, 5 Apr 2017 04:56:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751795AbdDEE4N (ORCPT ); Wed, 5 Apr 2017 00:56:13 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:59014 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751512AbdDEE4K (ORCPT ); Wed, 5 Apr 2017 00:56:10 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1515860F64; Wed, 5 Apr 2017 04:56:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1491368170; bh=X8HWnjAGhfYJ09c2j7NLZVPfDnwVTbOoCsz5lQQ9apk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KH+gnJbKBO3UIy4JbglZtGVnVnkRMzrJ7fwGvKpAUH2pvvbkmuNeDnXayQXc6gjw2 onIKFW5q0D2H1aa6cbJ1UmFlOwWira+D8g0k8Lw/EGlzMHCuSQ9nviKO6O77tIEhks s6d5lnpmDkVpR4R9R8soOAMFu9Ca+AxYOPoPE2A4= Received: from blr-ubuntu-173.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 953D960F5E; Wed, 5 Apr 2017 04:56:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1491368169; bh=X8HWnjAGhfYJ09c2j7NLZVPfDnwVTbOoCsz5lQQ9apk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J4Vp51AvLPdPfxdCK3MlYw+3EmkwO4vNivm8fNPL80M0C/DlXPpSklfcg+/rpO342 wVNDxuvOAB3c782zecF3Wj5ayH1vdQsvsR/TiUMCjg9paSHIn3JvExB5ZTWfIUzgoc 66Axs76HrDG6DL2gRhAc4aRcrhNw3mU2TN63pBb8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 953D960F5E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Rajendra Nayak Subject: [PATCH 5/6] clk: qcom: cpu-8996: Add support to switch below 600Mhz Date: Wed, 5 Apr 2017 10:25:28 +0530 Message-Id: <1491368129-24721-6-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491368129-24721-1-git-send-email-rnayak@codeaurora.org> References: <1491368129-24721-1-git-send-email-rnayak@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The CPU clock controllers primary PLL operates on a single VCO range, between 600Mhz and 3Ghz. However the CPUs do support OPPs with frequencies between 300Mhz and 600Mhz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600Mhz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300Mhz and 600Mhz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/clk-cpu-8996.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 9bb25be..79db4e8 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -28,6 +28,7 @@ #define PLL_INDEX 1 #define ACD_INDEX 2 #define ALT_INDEX 3 +#define DIV_2_THRESHOLD 600000000 /* PLLs */ @@ -121,6 +122,7 @@ struct clk_cpu_8996_mux { u32 width; struct notifier_block nb; struct clk_hw *pll; + struct clk_hw *pll_div_2; struct clk_regmap clkr; }; @@ -171,6 +173,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) if (!cpuclk->pll) return -EINVAL; + if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { + if (req->rate < (DIV_2_THRESHOLD / 2)) + return -EINVAL; + + parent = cpuclk->pll_div_2; + } + req->best_parent_rate = clk_hw_round_rate(parent, req->rate); req->best_parent_hw = parent; @@ -182,13 +191,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, { int ret; struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); + struct clk_notifier_data *cnd = data; switch (event) { case PRE_RATE_CHANGE: ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); break; case POST_RATE_CHANGE: - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX); + if (cnd->new_rate < DIV_2_THRESHOLD) + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + DIV_2_INDEX); + else + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + PLL_INDEX); break; default: ret = 0; @@ -241,6 +256,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -261,6 +277,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux",