From patchwork Fri Apr 21 17:19:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9693279 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 93A696038E for ; Fri, 21 Apr 2017 17:40:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8720928655 for ; Fri, 21 Apr 2017 17:40:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B8D62865C; Fri, 21 Apr 2017 17:40:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9595628655 for ; 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Fri, 21 Apr 2017 17:20:16 +0000 (GMT) X-AuditID: b6c32a59-f79166d0000017ce-c6-58fa3f519215 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 43.F8.05013.05F3AF85; Sat, 22 Apr 2017 02:20:16 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OOR00KJBS560G40@mmp1.samsung.com>; Sat, 22 Apr 2017 02:20:16 +0900 (KST) From: Sylwester Nawrocki To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org Cc: inki.dae@samsung.com, sw0312.kim@samsung.com, cw00.choi@samsung.com, javier@osg.samsung.com, krzk@kernel.org, jy0922.shim@samsung.com, broonie@kernel.org, robh+dt@kernel.org, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH RFC 1/7] clk: samsung: Add enable/disable operation for PLL36XX clocks Date: Fri, 21 Apr 2017 19:19:45 +0200 Message-id: <1492795191-31298-2-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAzWSe0hTYRjG/c7d2ewwbx8u/WMRpKA2STnRvaRWUmj94ZJoHfKgoptjU9Eg EUWX95EpKylHIV5SpmMuQbOcc94wtcQgUikULYwyL8XClfPM/37P+zzP+/LBR6EiJxZMpauy OY2KzZQQAsw6GBYWkXjaKT+y8VrAzEzbEKbLYMKZus+LBPNhYxlnGu1vcWZm8wfBPFjQY8zq 93aEWZmfxpjJyU6SWaucxxnDZD/ClLyyk8zgqm5H1n4lzuyXda4XETJzWxkhW6gYRmSWmjlS Vm1pA7J1c2gCkSw4kcJlpudymqhTtwVp5rU5XP0zPK96fAItBKaD5cCbgvRR+K+kmOA5EE7N m3ZYQInoJgDXtwpRXugQ+NJVROw1nnQ/9xjNADaNDWG8cAL4pWERdacIWgqrhqqB2/CnnwI4 a9XvLkZpF4D1U7WkO+VHy2FP7+guY/QhOPG7YrctpC/AZkcHyt8LhaOOWrwcUJQ3fRFOL5Hu PZC2krDkzyzinkM6BJrfeOJx0OXYJnn2g9+GLR4Ww+2mj4Dv1gA40l7sEQYAP+n0CJ86DgeH p3E3o7QvrPq76DkghPdLRXxEBk2/6gE/PgsNfdf51z8GsK91AdGDA0bg1QYCObVWmcppY9Qx kVpWqc1RpUbeyVKawe6PCL/RA2YeXbMBmgKSfcIWzCkX4WyuNl9pA5BCJf7C+KidkTCFzb/L abIUmpxMTmsDYgqTBAkPt87KRXQqm81lcJya0+y5COUdXAjIAYy9etPScKnOHN/l01ETN8Xa A/Iue40ds75vKW6MPVfQm6WQpvWOx5a6qIzokYL2lRBfe83m0kOHRZrQSj7DV/Qn3yUKy8gk PdrtE5Fy73ySUWUQVKr6X5j8FI0FI1sKndGnsCoopOEWKy4XX0kYGA0Ijs4FatK4nJEswbRp rDQc1WjZ/+deamENAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNIsWRmVeSWpSXmKPExsVy+t9jAd0A+18RBgs3GlpcuXiIyWLjjPWs FlMfPmGzuP7lOavF/CPnWC2ufH3PZjHp/gQWizdv1zBZvLh3kcXi/PkN7BYfe+6xWsw4v4/J onXvEXaLw2/agdzJL9kc+D02fG5i89i0qpPN4373cSaPLf132T36tqxi9Pi8SS6ALcrNJiM1 MSW1SCE1Lzk/JTMv3VYpNMRN10JJIS8xN9VWKULXNyRISaEsMacUyDMyQAMOzgHuwUr6dglu GZs+3mUt+KBV0Xf6LHMD43rlLkZODgkBE4m5WxczQ9hiEhfurWfrYuTiEBJYyihxbu1bFgjn F6NE6/WVjCBVbAKGEr1H+xhBEiIC8xglNpxcC+YwC/xjlDjW1M8CUiUsECEx88lRVhCbRUBV 4uz3brAdvAJuEsuPrYXaJydx8thkoBoODk4Bd4mLT9lBwkJAJUv7L7NOYORdwMiwilEitSC5 oDgpPdcoL7Vcrzgxt7g0L10vOT93EyM4Yp5J72A8vMv9EKMAB6MSD+8Kll8RQqyJZcWVuYcY JTiYlUR4vfWBQrwpiZVVqUX58UWlOanFhxhNge6ayCwlmpwPjOa8knhDE3MTc2MDC3NLSxMj JXHextnPwoUE0hNLUrNTUwtSi2D6mDg4pRoYPZ0ZHPQNU5r3nPZ6f3NDcqTsl1tOvOuMJ7Ye XWIs+lmXxWH6qRsRt1YKrr7wqe3oZfdLK2vffj5rmNfdLpj6jve+ataGmhVKX/Ld5J890o/h 9Hj5//W8nkMvuH8vNPqlqvN4unrNd7Hn8RzW0xKEPDfK9Pz1vs0qEfhm/pcNJflFP/pLjevL lViKMxINtZiLihMB37Vfs64CAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170421172016epcas5p342c16e1219c1205a44a84eaa770ad5ac X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-CMS-RootMailID: 20170421172016epcas5p342c16e1219c1205a44a84eaa770ad5ac X-RootMTR: 20170421172016epcas5p342c16e1219c1205a44a84eaa770ad5ac References: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The existing enable/disable ops for PLL35XX are made more generic and used also for PLL36XX. This fixes issues in the kernel with PLL36XX PLLs when the PLL has not been already enabled by bootloader. Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-pll.c | 85 +++++++++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 36 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5229089..10c76eb 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -23,6 +23,10 @@ struct samsung_clk_pll { struct clk_hw hw; void __iomem *lock_reg; void __iomem *con_reg; + /* PLL enable control bit offset in @con_reg register */ + unsigned short enable_offs; + /* PLL lock status bit offset in @con_reg register */ + unsigned short lock_offs; enum samsung_pll_type type; unsigned int rate_count; const struct samsung_pll_rate_table *rate_table; @@ -61,6 +65,34 @@ static long samsung_pll_round_rate(struct clk_hw *hw, return rate_table[i - 1].rate; } +static int samsung_pll3xxx_enable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp |= BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); + + /* wait lock time */ + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(pll->lock_offs))); + + return 0; +} + +static void samsung_pll3xxx_disable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp |= BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); +} + /* * PLL2126 Clock Type */ @@ -142,34 +174,6 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, #define PLL35XX_LOCK_STAT_SHIFT (29) #define PLL35XX_ENABLE_SHIFT (31) -static int samsung_pll35xx_enable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp |= BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); - - /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); - - return 0; -} - -static void samsung_pll35xx_disable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp &= ~BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); -} - static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -239,11 +243,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(tmp, pll->con_reg); /* wait_lock_time if enabled */ - if (tmp & BIT(PLL35XX_ENABLE_SHIFT)) { + if (tmp & BIT(pll->enable_offs)) { do { cpu_relax(); tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); + } while (!(tmp & BIT(pll->lock_offs))); } return 0; } @@ -252,8 +256,8 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, .recalc_rate = samsung_pll35xx_recalc_rate, .round_rate = samsung_pll_round_rate, .set_rate = samsung_pll35xx_set_rate, - .enable = samsung_pll35xx_enable, - .disable = samsung_pll35xx_disable, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll35xx_clk_min_ops = { @@ -275,6 +279,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, #define PLL36XX_SDIV_SHIFT (0) #define PLL36XX_KDIV_SHIFT (0) #define PLL36XX_LOCK_STAT_SHIFT (29) +#define PLL36XX_ENABLE_SHIFT (31) static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -354,10 +359,12 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(pll_con1, pll->con_reg + 4); /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); + if (pll_con0 & BIT(pll->enable_offs)) { + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(PLL36XX_LOCK_STAT_SHIFT))); + } return 0; } @@ -366,6 +373,8 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, .recalc_rate = samsung_pll36xx_recalc_rate, .set_rate = samsung_pll36xx_set_rate, .round_rate = samsung_pll_round_rate, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll36xx_clk_min_ops = { @@ -1288,6 +1297,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1450x: case pll_1451x: case pll_1452x: + pll->enable_offs = PLL35XX_ENABLE_SHIFT; + pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1306,6 +1317,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 36xx and 2650 are similar */ case pll_36xx: case pll_2650: + pll->enable_offs = PLL36XX_ENABLE_SHIFT; + pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll36xx_clk_min_ops; else