From patchwork Mon May 15 11:55:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 9726759 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0E55560380 for ; Mon, 15 May 2017 11:55:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E9D0728999 for ; Mon, 15 May 2017 11:55:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E5C65289AA; Mon, 15 May 2017 11:55:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C5E1928999 for ; Mon, 15 May 2017 11:55:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755585AbdEOLzZ (ORCPT ); Mon, 15 May 2017 07:55:25 -0400 Received: from mail-qt0-f196.google.com ([209.85.216.196]:36805 "EHLO mail-qt0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755045AbdEOLzY (ORCPT ); Mon, 15 May 2017 07:55:24 -0400 Received: by mail-qt0-f196.google.com with SMTP id j13so14993190qta.3 for ; Mon, 15 May 2017 04:55:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=mqU1J+kdd7eEitc/RFp51X0WD1JReogEAWzsnEkjSp0=; b=n7Dl9XbblKzMN0cuhB7BQleHHjgGRmWomqa7zxhorWdcLCu/04iXl1chzhzZvp4bEk 5mL7IF2N30dlLSaeIjFRhA6Ec/4dL0ZLv/1NaAcmnDJwW9Q7KKTHdzZOyDZtpJKZuJaw Q96i3DnC5bTtUqjjyDF9fkytL4yXeV5C4kXGgBZdoQ4Gwgexx5+xB2SzJAxNaPG4DcA9 jQNP5mCrk2qtKOpaRu7Wrr5uxY2s6OgGSrp4IWahhD2Zxbz6USoaOkA8toXXGC+ftuK3 C7bjhOBAggVPhwZ8pdLd+zIgV3rHG/WPJEC6tBeSTLcPUeX68ma/BaPYM8ava4EG1M7E bIlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=mqU1J+kdd7eEitc/RFp51X0WD1JReogEAWzsnEkjSp0=; b=h7Qxhbd3LDXXvsRCGlPgKUJd5rPMu2N4JVGGJP4ky7HvUis2NOoL16TOw7ftlKeqCZ InYKNO8b5zYgDLNTU3gSeDlFHxw2GkAZwUNUfZ1DmPy8woqQOYvfTlbXS9pKfeR6N/Xf 3m/KiojkNy7CgOhfAt3JVkz4a61dfZSNtr4HE17dehQnGyfd/eH/tqwbJt/2lYcGMuPf EBy6T/O/5BjmcEYhF2DNN+oTV5nPcbGa6YSKEVI3OJvG5pFw4V+OYD0bEix5upAmfBgs W6fkY8EwAHWF1Z3pieptYydkTVcLxxmcL9Lp0HQ7nw/W9DmtjZQfDXXwgvhppppc0074 Do3A== X-Gm-Message-State: AODbwcBj9rK0Lb9GC4roU91IT/jgw56Bo5FIMG8ShTrOVq4mozgzwRXT nszA4xiVIYd64Q== X-Received: by 10.237.63.37 with SMTP id p34mr5423456qtf.73.1494849324024; Mon, 15 May 2017 04:55:24 -0700 (PDT) Received: from localhost.localdomain ([187.180.182.83]) by smtp.gmail.com with ESMTPSA id b77sm8126380qkj.47.2017.05.15.04.55.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 May 2017 04:55:23 -0700 (PDT) From: Fabio Estevam To: sboyd@codeaurora.org Cc: shawnguo@kernel.org, kernel@pengutronix.de, linux-clk@vger.kernel.org, stefan@agner.ch, Fabio Estevam Subject: [PATCH v2] clk: imx7d: Fix the powerdown bit location of PLL DDR Date: Mon, 15 May 2017 08:55:05 -0300 Message-Id: <1494849305-1405-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 2.7.4 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Fabio Estevam According to the MX7D Reference Manual the powerdown bit of CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly. Signed-off-by: Fabio Estevam Reviewed-by: Stefan Agner --- Changes since v1: - Rename to IMX7_DDR_PLL_POWER to make it consistent with the other special case for the powerdown bit (IMX7_ENET_PLL_POWER) - Stefan drivers/clk/imx/clk-imx7d.c | 2 +- drivers/clk/imx/clk-pllv3.c | 5 +++++ drivers/clk/imx/clk.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 93b0364..8fa1841 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -424,7 +424,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f); - clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_dram_main", "osc", base + 0x70, 0x7f); + clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f); clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1); clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0); clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f); diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index f109916..0039b16 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -27,6 +27,7 @@ #define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) #define IMX7_ENET_PLL_POWER (0x1 << 5) +#define IMX7_DDR_PLL_POWER (0x1 << 20) /** * struct clk_pllv3 - IMX PLL clock version 3 @@ -451,6 +452,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->ref_clock = 500000000; ops = &clk_pllv3_enet_ops; break; + case IMX_PLLV3_DDR_IMX7: + pll->power_bit = IMX7_ENET_PLL_POWER; + ops = &clk_pllv3_av_ops; + break; default: ops = &clk_pllv3_ops; } diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index e1f5e42..d54f072 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -35,6 +35,7 @@ enum imx_pllv3_type { IMX_PLLV3_ENET, IMX_PLLV3_ENET_IMX7, IMX_PLLV3_SYS_VF610, + IMX_PLLV3_DDR_IMX7, }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,