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Thu, 8 Jun 2017 14:17:22 +0000 (GMT) X-AuditID: b6c32a2e-f79506d0000046c0-1a-59395c733541 Received: from epmmp1.local.host ( [203.254.227.16]) by epsmgms2p2.samsung.com (Symantec Messaging Gateway) with SMTP id BA.19.02294.27C59395; Thu, 8 Jun 2017 23:17:22 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OR800JEXFORBW80@mmp1.samsung.com>; Thu, 08 Jun 2017 23:17:22 +0900 (KST) From: Sylwester Nawrocki To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: cw00.choi@samsung.com, krzk@kernel.org, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Date: Thu, 08 Jun 2017 16:17:11 +0200 Message-id: <1496931433-5712-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPIsWRmVeSWpSXmKPExsWy7bCmhm5xjGWkwaKlshYbZ6xntbj+5Tmr xfnzG9gtPvbcY7WYcX4fk8XhN+2sDmwem1Z1snn0bVnF6PF5k1wAcxSXTUpqTmZZapG+XQJX xupdq9gLnulU9P14wdbA+F+li5GTQ0LAROLuutlsELaYxIV764FsLg4hgaWMEu//vmKCcD4z SrTPvs/cxcgB1nH1TyhEfAejxK+Wx8wQzi9GiZ+7TzKCjGITMJToPdoHZosIOEjsOjaZCcRm FiiWWPd+GpgtLBAisebMBlYQm0VAVeLblN0sIAt4BVwl/m6yg7hITuLkscmsIPMlBLawSUz8 3cgOcYSsxKYDzBA1LhJP/r9mhLCFJV4d38IOYUtJdHfMYofo7WeUOLGmmRHCmcEocad9AhNE lbXE4eMXWSGO45Po/f2ECWIBr0RHmxBEiYfEggv7WCFsR4mTb9eBLRASiJU429fGPoFRegEj wypGsdSC4tz01GLTAmO94sTc4tK8dL3k/NxNjOBo1NLbwfhvgfchRgEORiUeXo4wy0gh1sSy 4srcQ4wSHMxKIrxHDYBCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeTVWXosQEkhPLEnNTk0tSC2C yTJxcEo1ME7I6rzeIWJzcf9S1ZAuwSKRu85T5funhjSELTRXDntbx8O2ITzgm2XVs+fbJyVL /Yz74W693ujCmS/Po8IyFUT1HF7NUln/8kX/0XTnCSma545kCc84uKte9NsLM7P4bwr/OhPs Uyr8li5UzVIzFtVNkC2t2PpDVnSzR+S/8sXnHW4m2jvPVmIpzkg01GIuKk4EAACj/JHCAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGLMWRmVeSWpSXmKPExsVy+t9jAd2iGMtIg9VTpSw2zljPanH9y3NW i/PnN7BbfOy5x2ox4/w+JovDb9pZHdg8Nq3qZPPo27KK0ePzJrkA5ig3m4zUxJTUIoXUvOT8 lMy8dFul0BA3XQslhbzE3FRbpQhd35AgJYWyxJxSIM/IAA04OAe4Byvp2yW4ZazetYq94JlO Rd+PF2wNjP9Vuhg5OCQETCSu/gntYuQEMsUkLtxbz9bFyMUhJLCNUaJp9wRmCOcXo8Smv5fZ QarYBAwleo/2MYLYIgIOEruOTWYCsZkFiiXe9t5kBbGFBUIk1pzZAGazCKhKfJuymwVkGa+A q8TfTXYQy+QkTh6bzDqBkXsBI8MqRq7UguLc9NxiowKjTYzAMNt2WCtgB2PTuehDjAIcjEo8 vAkRlpFCrIllxZW5hxglOJiVRHiPGgCFeFMSK6tSi/Lji0pzUosPMZoCbZzILCWanA+MgbyS eEMTSyMTAzMzQyMDYzMlcd4JgV8ihATSE0tSs1NTC1KLYPqYODilGhilKjqX6L5/0GYk9JTd f9mCPr7T/xu/LF20Yhe/51yDk0zlSk2KU1XPLFl1+kCPgJuQgy27jEz57x32+r352zgDv1+8 rxKv/shr5Y8zSQd1Tk0yLivTiT1ZWvhq7upjp1bO35Sg7Gxo2nzX5dS0x2Vqy17PL+Ra6yl8 w/3qdMN78XvjNi+MV8hUYinOSDTUYi4qTgQAot5xC0kCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170608141722epcas5p2310095ad549f30841430f5cc3e364908 X-Msg-Generator: CA X-Sender-IP: 182.195.42.80 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-CMS-RootMailID: 20170608141722epcas5p2310095ad549f30841430f5cc3e364908 X-RootMTR: 20170608141722epcas5p2310095ad549f30841430f5cc3e364908 References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The existing enable/disable ops for PLL35XX are made more generic and used also for PLL36XX. This fixes issues in the kernel with PLL36XX PLLs when the PLL has not been already enabled by bootloader. Signed-off-by: Sylwester Nawrocki Reviewed-by: Chanwoo Choi Tested-by: Chanwoo Choi --- Changes since RFC version: - fixed wrong bit handling in samsung_pll3xxx_disable() - pll->lock_offs used and comment improved in samsung_pll35xx_set_rate() --- drivers/clk/samsung/clk-pll.c | 87 +++++++++++++++++++++++++------------------ 1 file changed, 50 insertions(+), 37 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5229089..5c4899c 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -23,6 +23,10 @@ struct samsung_clk_pll { struct clk_hw hw; void __iomem *lock_reg; void __iomem *con_reg; + /* PLL enable control bit offset in @con_reg register */ + unsigned short enable_offs; + /* PLL lock status bit offset in @con_reg register */ + unsigned short lock_offs; enum samsung_pll_type type; unsigned int rate_count; const struct samsung_pll_rate_table *rate_table; @@ -61,6 +65,34 @@ static long samsung_pll_round_rate(struct clk_hw *hw, return rate_table[i - 1].rate; } +static int samsung_pll3xxx_enable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp |= BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); + + /* wait lock time */ + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(pll->lock_offs))); + + return 0; +} + +static void samsung_pll3xxx_disable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp &= ~BIT(pll->enable_offs); + writel_relaxed(tmp, pll->con_reg); +} + /* * PLL2126 Clock Type */ @@ -142,34 +174,6 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, #define PLL35XX_LOCK_STAT_SHIFT (29) #define PLL35XX_ENABLE_SHIFT (31) -static int samsung_pll35xx_enable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp |= BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); - - /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); - - return 0; -} - -static void samsung_pll35xx_disable(struct clk_hw *hw) -{ - struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 tmp; - - tmp = readl_relaxed(pll->con_reg); - tmp &= ~BIT(PLL35XX_ENABLE_SHIFT); - writel_relaxed(tmp, pll->con_reg); -} - static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -238,12 +242,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL35XX_SDIV_SHIFT); writel_relaxed(tmp, pll->con_reg); - /* wait_lock_time if enabled */ - if (tmp & BIT(PLL35XX_ENABLE_SHIFT)) { + /* Wait until the PLL is locked if it is enabled. */ + if (tmp & BIT(pll->enable_offs)) { do { cpu_relax(); tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); + } while (!(tmp & BIT(pll->lock_offs))); } return 0; } @@ -252,8 +256,8 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, .recalc_rate = samsung_pll35xx_recalc_rate, .round_rate = samsung_pll_round_rate, .set_rate = samsung_pll35xx_set_rate, - .enable = samsung_pll35xx_enable, - .disable = samsung_pll35xx_disable, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll35xx_clk_min_ops = { @@ -275,6 +279,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, #define PLL36XX_SDIV_SHIFT (0) #define PLL36XX_KDIV_SHIFT (0) #define PLL36XX_LOCK_STAT_SHIFT (29) +#define PLL36XX_ENABLE_SHIFT (31) static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -354,10 +359,12 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(pll_con1, pll->con_reg + 4); /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); + if (pll_con0 & BIT(pll->enable_offs)) { + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(pll->lock_offs))); + } return 0; } @@ -366,6 +373,8 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, .recalc_rate = samsung_pll36xx_recalc_rate, .set_rate = samsung_pll36xx_set_rate, .round_rate = samsung_pll_round_rate, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, }; static const struct clk_ops samsung_pll36xx_clk_min_ops = { @@ -1288,6 +1297,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1450x: case pll_1451x: case pll_1452x: + pll->enable_offs = PLL35XX_ENABLE_SHIFT; + pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1306,6 +1317,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 36xx and 2650 are similar */ case pll_36xx: case pll_2650: + pll->enable_offs = PLL36XX_ENABLE_SHIFT; + pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; if (!pll->rate_table) init.ops = &samsung_pll36xx_clk_min_ops; else