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Thu, 8 Jun 2017 14:17:26 +0000 (GMT) X-AuditID: b6c32a39-f790c6d000000e85-6f-59395c772c44 Received: from epmmp1.local.host ( [203.254.227.16]) by epsmgms2p1.samsung.com (Symantec Messaging Gateway) with SMTP id A7.DF.02179.67C59395; Thu, 8 Jun 2017 23:17:26 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OR800JEXFORBW80@mmp1.samsung.com>; Thu, 08 Jun 2017 23:17:26 +0900 (KST) From: Sylwester Nawrocki To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: cw00.choi@samsung.com, krzk@kernel.org, b.zolnierkie@samsung.com, Sylwester Nawrocki Subject: [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks Date: Thu, 08 Jun 2017 16:17:12 +0200 Message-id: <1496931433-5712-2-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1496931433-5712-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDIsWRmVeSWpSXmKPExsWy7bCmnm55jGWkwb8jWhYbZ6xntbj+5Tmr xfnzG9gtPvbcY7WYcX4fk8XhN+2sDmwem1Z1snn0bVnF6PF5k1wAcxSXTUpqTmZZapG+XQJX Rk9nO1PBP6mKed0PmBsYp4l3MXJySAiYSLx92M8MYYtJXLi3nq2LkYtDSGAHo8T3O+fZIZzP jBJH9ixjhOmYsryfCa5qzqX/UFW/GCUaf11kBaliEzCU6D3aB9YhIuAgsevYZCYQm1mgWGLd +2lANgeHsECAxO5pgiBhFgFViYb2D2Bn8Aq4Sty+cZwNYpmcxMljk8FGcgq4SRx9fYQFZJeE wAk2iV3rl7CCzJEQkJXYdIAZwnSRONeuC9EqLPHq+BZ2CFtKovHlQyaI1n5GiRNrmhkhnBmM EnfaJzBBVFlLHD4OcT+zAJ/Eu689UPN5JTrahCBKPCSufXjLAmE7Sszf8ZcF4veZjBKdF/4x TWCUWcDIsIpRLLWgODc9tdiwwFSvODG3uDQvXS85P3cTIzhOtSx3MB4753OIUYCDUYmHNyHC MlKINbGsuDL3EKMEB7OSCO9RA6AQb0piZVVqUX58UWlOavEhRmkOFiVxXtH11yKEBNITS1Kz U1MLUotgskwcnFINjOsnrXTvd3kv86osftqUbbvbsmzbGDlYRKwz1Ka9T7PQWdwrasOiziy5 ZqJLh+PyhJ9vfFc3985ImtbuXHxvYavh5ZUGzRe23NH793NHw4tVK6JMLt8uktwy5UXaqpkd DzN7HZJ0fs84s7W166mp3t+ANZNOP+eXPrMwxmCnmUjzRoY//qc+aSqxFGckGmoxFxUnAgAr JN+2zwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsVy+t9jAd2yGMtIg+vz9Sw2zljPanH9y3NW i/PnN7BbfOy5x2ox4/w+JovDb9pZHdg8Nq3qZPPo27KK0ePzJrkA5ig3m4zUxJTUIoXUvOT8 lMy8dFul0BA3XQslhbzE3FRbpQhd35AgJYWyxJxSIM/IAA04OAe4Byvp2yW4ZfR0tjMV/JOq mNf9gLmBcZp4FyMnh4SAicSU5f1MELaYxIV769m6GLk4hAS2MUpMXTmXFcL5xSjxpusCM0gV m4ChRO/RPkYQW0TAQWLXsclg3cwCxRJve2+ygtjCAn4Sl27NBKthEVCVaGj/ANbLK+AqcfvG cTaIbXISJ49NBqvnFHCTOPr6CAuILQRUM7mtgWkCI+8CRoZVjFypBcW56bnFRgWGmxiBobnt sJb/DsYfZ6MPMQpwMCrx8CZEWEYKsSaWFVfmHmKU4GBWEuE9agAU4k1JrKxKLcqPLyrNSS0+ xGgKdMpEZinR5Hxg3OSVxBuaWBqZGJiZGRoZGJspifNOCPwSISSQnliSmp2aWpBaBNPHxMEp 1cAoM2UGV9vaKzY6t9R/qOwNmlK6Kft+zAQrlQ8hUXFXlVPmVGlyJXxeWnMi+n+984XAg9p7 H9Ywb12/S9UteP42FznP3Y05V/vDz+p8OXj0znXm1axnQsu7Uo5/vpGSFsEQuTYtYv+lVscs +ZLD95T0hLc/bWDcURnZP2XFzp39+a6M6a4Lu2SUWIozEg21mIuKEwEK0tSQYwIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170608141726epcas1p1ab3faf22e9f398ae4cf23f84f487d123 X-Msg-Generator: CA X-Sender-IP: 182.195.42.79 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 101P X-CMS-RootMailID: 20170608141726epcas1p1ab3faf22e9f398ae4cf23f84f487d123 X-RootMTR: 20170608141726epcas1p1ab3faf22e9f398ae4cf23f84f487d123 References: <1496931433-5712-1-git-send-email-s.nawrocki@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds missing definitions of mux clocks required for using EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs. Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Tested-by: Chanwoo Choi --- Changes since RFC version: - dropped one clean up chunk --- drivers/clk/samsung/clk-exynos5420.c | 10 +++++++--- include/dt-bindings/clock/exynos5420.h | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index cdc092a..6f1d6c0 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -487,6 +487,7 @@ static void __init exynos5420_clk_sleep_init(void) {} PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; +PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock @@ -536,8 +537,8 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), - MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, - 20, 2), + MUX(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, + SRC_TOP7, 20, 2), MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), @@ -546,6 +547,8 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), + MUX(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, + SRC_TOP9, 8, 1), MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, SRC_TOP9, 16, 1), MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, @@ -703,7 +706,7 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), - MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), + MUX(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), @@ -1399,6 +1402,7 @@ static void __init exynos5x_clk_init(struct device_node *np, if (_get_rate("fin_pll") == 24 * MHZ) { exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; } diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 6fd21c2..2740ae0 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -217,6 +217,9 @@ #define CLK_MOUT_MCLK_CDREX 654 #define CLK_MOUT_BPLL 655 #define CLK_MOUT_MX_MSPLL_CCORE 656 +#define CLK_MOUT_EPLL 657 +#define CLK_MOUT_MAU_EPLL 658 +#define CLK_MOUT_USER_MAU_EPLL 659 /* divider clocks */ #define CLK_DOUT_PIXEL 768