From patchwork Thu Jul 6 10:24:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 9827981 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0576A60317 for ; Thu, 6 Jul 2017 10:25:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EABF5285E2 for ; Thu, 6 Jul 2017 10:25:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DF37228607; Thu, 6 Jul 2017 10:25:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1786C28604 for ; Thu, 6 Jul 2017 10:25:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752580AbdGFKZk (ORCPT ); Thu, 6 Jul 2017 06:25:40 -0400 Received: from mail-wr0-f175.google.com ([209.85.128.175]:33327 "EHLO mail-wr0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752340AbdGFKYj (ORCPT ); Thu, 6 Jul 2017 06:24:39 -0400 Received: by mail-wr0-f175.google.com with SMTP id r103so22713625wrb.0 for ; Thu, 06 Jul 2017 03:24:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kmsO2YpX20AbzIOdEHie/4Q4l+kqgrI8eY2t0a4GUcs=; b=VH1HWrzm78GhKjw6G83HJ6c+B2jbBDPw5dn4Z/ITqBcdvYpqMxXTmNTfBhPbTpe8j6 aoGt6ZauWYLNM4+1cu69jKWdLA8QBsFy0NPi31pnp03YpEx5Efrf7YOB8zE0xQLR8oTT 7SZb7VBLc8QoGmP7eZTt8wzvdDQ7Lx4/059cnH6T2bT9vqrlQx+6CMVIZbUIyDdLiBpa jiU0JR11goBIZeV2wwoCnRso8fh6Tp7r7r0VW0rwYdGtAMpnkhoaukhft9SXSZeholZe g1VcXMyouk1gNYDWJzW6SbsBxjYWfVj1yBgtFKB1C49BZbKbzda138N3T1hQznueNn9y KU1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kmsO2YpX20AbzIOdEHie/4Q4l+kqgrI8eY2t0a4GUcs=; b=OJtcdJ0+cOsrveDUs+Zyrl9X49ixtP9sZDbr82YnJth+GF9kSqsMe9IfwogVU+XmUW h/4R1BTTCZIB5t44ejIusWA5I6v7hvxfmSlrlR0xmQ6RUqLSwpBq5qQ0pX2a5Z+ApEjC I2vd+MXNg5YprZmoAHjhZgkbxaKtv5fpqz/aC1twI1C/SzhXvnrXd+rZVIGlcCLOOjO9 rN8uwMDq5JexlYSwpzxSZxaYtmmwMYpl1nToGymkUNHxIJJ6Jh1XoSDgidrXAP5EeCfd 7ELrKmtN7mmrhHZpzdg5cHcTismnN8316GjMSFKos0u6pIUATek8HjkSfsixpJ4/oU/l 3NfQ== X-Gm-Message-State: AKS2vOxdTyXqAwnl1VtAhXGpnCXOpxv9HkHgCcTlrK5o1AHOPGG/Stwr 57oVvAiteQ2URiwo X-Received: by 10.223.174.194 with SMTP id y60mr46896862wrc.19.1499336678492; Thu, 06 Jul 2017 03:24:38 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id w197sm31936286wme.20.2017.07.06.03.24.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Jul 2017 03:24:37 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/3] dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings Date: Thu, 6 Jul 2017 12:24:23 +0200 Message-Id: <1499336663-23875-4-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499336663-23875-1-git-send-email-narmstrong@baylibre.com> References: <1499336663-23875-1-git-send-email-narmstrong@baylibre.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On the first revision of the bindings, only the gates + resets were known in the AO Clock HW, but more registers used to configures AO clock are known to be spread among the AO register space. This patch adds these registers to the Ao Clock bindings with direct access and shared extcon access. Signed-off-by: Neil Armstrong Acked-by: Rob Herring --- .../devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index a55d31b..5c5ccec 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -7,7 +7,10 @@ Required Properties: - compatible: should be "amlogic,gxbb-aoclkc" - reg: physical base address of the clock controller and length of memory - mapped region. + mapped region for each registers listed in reg-names. +- reg-names: should contain the following register names : + "aoclk", "aocrt" and "aortc". +- amlogic,pwr-ctrl: A phandle to the AO Power Control node. - #clock-cells: should be 1. @@ -27,9 +30,13 @@ Example: AO Clock controller node: clkc_AO: clock-controller@040 { compatible = "amlogic,gxbb-aoclkc"; - reg = <0x0 0x040 0x0 0x4>; + reg = <0x0 0x00040 0x0 0x4>, + <0x0 0x00068 0x0 0x4>, + <0x0 0x00094 0x0 0x8>; + reg-names = "aoclk", "aocrt", "aortc"; #clock-cells = <1>; #reset-cells = <1>; + amlogic,pwr-ctrl = <&pwr_AO>; }; Example: UART controller node that consumes the clock and reset generated