From patchwork Fri Jul 21 11:19:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9856643 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7202960388 for ; Fri, 21 Jul 2017 11:20:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A6EF28783 for ; Fri, 21 Jul 2017 11:20:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4F2362879A; Fri, 21 Jul 2017 11:20:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B52B28786 for ; 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Fri, 21 Jul 2017 11:20:08 +0000 (GMT) X-AuditID: b6c32a2e-f79746d00000129a-5a-5971e368848a Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p2.samsung.com (Symantec Messaging Gateway) with SMTP id 2A.05.05071.863E1795; Fri, 21 Jul 2017 20:20:08 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OTF006FBU5B1A10@mmp2.samsung.com>; Fri, 21 Jul 2017 20:20:08 +0900 (KST) From: Sylwester Nawrocki To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: cw00.choi@samsung.com, krzk@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, Sylwester Nawrocki Subject: [PATCH] clk: samsung: exynos5420: The EPLL rate table corrections Date: Fri, 21 Jul 2017 13:19:50 +0200 Message-id: <1500635990-19474-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFIsWRmVeSWpSXmKPExsWy7bCmpm7G48JIg85uTYuNM9azWlz/8pzV 4vz5DewWH3vusVpc3jWHzWLG+X1MFhdPuVocftPOavHjTDeLA6fH+xut7B6X+3qZPDat6mTz 6NuyitHj8ya5ANYoLpuU1JzMstQifbsErozNtz6xFzQJVezd942tgXE6fxcjJ4eEgInE2snP GCFsMYkL99azdTFycQgJLGWUOPfnPAuE85lR4tPDTlaYjhcbZzBDJNYySiye1g7V8otR4sf9 b0wgVWwChhK9R/vA5ooA2csn7ATrYBa4zChxrb2fDSQhLOAl8WnvXmYQm0VAVeJWzxcWEJtX wE3i74av7BDr5CROHpvMCtIsIXCdTWLatZNAzRxAjqzEpgPMEDUuEg3nbrJB2MISr45vgeqV kujumMUO0dvPKHFiTTMjhDODUeJO+wQmiCpricPHL4I9xyzAJ9H7+wkTxAJeiY42IYgSD4nF Pw9ALXCU+H6sC2yxkECsxM7zR9gnMEovYGRYxSiWWlCcm55abFpgrFecmFtcmpeul5yfu4kR HMNaejsY/y3wPsQowMGoxMPLsK4gUog1say4MvcQowQHs5IIb/7Dwkgh3pTEyqrUovz4otKc 1OJDjNIcLErivBorr0UICaQnlqRmp6YWpBbBZJk4OKUaGFsv1Hyx3HOsO/i5SnJPnkqfpv/e 5buUOdZwJnzuWC4e+GLplv7bW55ymatmH1q0K1fHetFn7ScPLQ8t3nFkrnp+0fy77Ed+anvm /A3JmvaqvP6frvg2BSOGhT4B757ZuTCpPk7a4ey0Ye1xg+kyEg/mZl3OTWfIPqGV8+jFw/V/ Lnev2jbDaLUSS3FGoqEWc1FxIgCYV7ni3QIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsVy+t9jQd2Mx4WRBrMn81tsnLGe1eL6l+es FufPb2C3+Nhzj9Xi8q45bBYzzu9jsrh4ytXi8Jt2VosfZ7pZHDg93t9oZfe43NfL5LFpVSeb R9+WVYwenzfJBbBGudlkpCampBYppOYl56dk5qXbKoWGuOlaKCnkJeam2ipF6PqGBCkplCXm lAJ5RgZowME5wD1YSd8uwS1j861P7AVNQhV7931ja2Cczt/FyMkhIWAi8WLjDGYIW0ziwr31 bF2MXBxCAqsZJZqun2UFSQgJ/GKUuNsXBWKzCRhK9B7tYwSxRYDs5RN2MoM0MAtcZJRYvvwg WIOwgJfEp717waayCKhK3Or5wgJi8wq4Sfzd8JUdYpucxMljk1knMHIvYGRYxciVWlCcm55b bFRgtIkRGJrbDmsF7GBsOhd9iFGAg1GJh5dhXUGkEGtiWXFl7iFGCQ5mJRHe/IeFkUK8KYmV ValF+fFFpTmpxYcYTYFWTmSWEk3OB8ZNXkm8oYmlkYmBmZmhkYGxmZI474TALxFCAumJJanZ qakFqUUwfUwcnFINjBslq9Q3yzN1Rdmm8d+obD1t8z604cknve8PNnjEuZVen6RR17lWJW2x vuG5lzrCa7brfhP5pyTSsIjh5bN3xVqhMlJ2mqFq17ak2vVYaSz0XMifNWc3g51ErqsB7/l8 /570PSxXzmz8UZZzs2tV33m1W+ZhU/+uPj2L69D33g8bGE0sq7/nKbEUZyQaajEXFScCAPDO UJBjAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170721112008epcas5p1eb75e4eb00d1dbad130460d2cbc0ce0c X-Msg-Generator: CA X-Sender-IP: 182.195.42.80 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-CMS-RootMailID: 20170721112008epcas5p1eb75e4eb00d1dbad130460d2cbc0ce0c X-RootMTR: 20170721112008epcas5p1eb75e4eb00d1dbad130460d2cbc0ce0c References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fixes values of the EPLL K coefficient and changes the EPLL output frequency values to match exactly what is possible to achieve with given M, P, S, K coefficients. This allows to avoid rounding errors and unexpected frequency being set with clk_set_rate(), due to recalc_rate returning different values than the PLL rate specified in the exynos5420_epll_24mhz_tbl table. E.g. this prevents a case where two consecutive clk_set_rate() calls with same argument result in different PLL output frequency. The PLL output frequencies have been calculated with formula: f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16 where fxtal = 24000000. Fixes: 9842452acd ("clk: samsung: exynos542x: Add EPLL rate table") Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 0748a0b..9a6476a 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1283,16 +1283,16 @@ static void __init exynos5420_clk_sleep_init(void) {} static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(600000000U, 100, 2, 1, 0), PLL_36XX_RATE(400000000U, 200, 3, 2, 0), - PLL_36XX_RATE(393216000U, 197, 3, 2, 25690), - PLL_36XX_RATE(361267200U, 301, 5, 2, 3671), + PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), + PLL_36XX_RATE(361267218U, 301, 5, 2, 3671), PLL_36XX_RATE(200000000U, 200, 3, 3, 0), - PLL_36XX_RATE(196608000U, 197, 3, 3, -25690), - PLL_36XX_RATE(180633600U, 301, 5, 3, 3671), - PLL_36XX_RATE(131072000U, 131, 3, 3, 4719), + PLL_36XX_RATE(196608001U, 197, 3, 3, -25690), + PLL_36XX_RATE(180633609U, 301, 5, 3, 3671), + PLL_36XX_RATE(131072006U, 131, 3, 3, 4719), PLL_36XX_RATE(100000000U, 200, 3, 4, 0), - PLL_36XX_RATE(65536000U, 131, 3, 4, 4719), - PLL_36XX_RATE(49152000U, 197, 3, 5, 25690), - PLL_36XX_RATE(32768000U, 131, 3, 5, 4719), + PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719), + PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690), + PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719), }; static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {