From patchwork Fri Jul 21 16:36:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9857309 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1340860392 for ; Fri, 21 Jul 2017 16:38:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F388B28621 for ; Fri, 21 Jul 2017 16:38:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E67402864A; Fri, 21 Jul 2017 16:38:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64C5B28621 for ; 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Fri, 21 Jul 2017 16:37:55 +0000 (GMT) X-AuditID: b6c32a36-f79db6d000001a5e-11-59722de4dc0b Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p1.samsung.com (Symantec Messaging Gateway) with SMTP id 72.BE.05076.3ED22795; Sat, 22 Jul 2017 01:37:55 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OTG0066Z8TJ1AB0@mmp2.samsung.com>; Sat, 22 Jul 2017 01:37:55 +0900 (KST) From: Sylwester Nawrocki To: linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@codeaurora.org, cw00.choi@samsung.com, krzk@kernel.org, linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, Sylwester Nawrocki Subject: [PATCH 3/3] clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL Date: Fri, 21 Jul 2017 18:36:44 +0200 Message-id: <1500655004-29816-3-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1500655004-29816-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOIsWRmVeSWpSXmKPExsWy7bCmnu4T3aJIgw+nuS02zljPanH9y3NW i/PnN7BbfOy5x2pxedccNosZ5/cxWVw85Wpx+E07q8WPM90sDpwe72+0sntc7utl8ti0qpPN o2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDKWzJvCVDBdsuLFqx3sDYwbRLsYOTkkBEwkvjcd ZYWwxSQu3FvP1sXIxSEksINRYtKKtywQzmdGiT9HNzDCdMxceZMZIrGWUeLir35WCOcXo8TG 9b9ZQKrYBAwleo/2gXWICMhK3Dr2E2wus8BzRolNT1aAJYQFYiV6fp9lB7FZBFQlbs7qYQOx eQXcJI7OWcwCsU5O4uSxyWAHcgq4S+z4fhnsJgmB92wSLw7cBrqDA8iRldh0gBmi3kViTtNV JghbWOLV8S3sELaUROPLh0wQvf2MEifWNDNCODMYJe60T4DqsJY4fPwi2DZmAT6Jd197WCEW 8Ep0tAlBlHhIvL3xH6rcUeLP5UtQ789ilHi4uJdlAqPMAkaGVYxiqQXFuempxYYFRnrFibnF pXnpesn5uZsYwdGtZbaDcdE5n0OMAhyMSjy8BixFkUKsiWXFlbmHGCU4mJVEeDfoAIV4UxIr q1KL8uOLSnNSiw8xSnOwKInziq6/FiEkkJ5YkpqdmlqQWgSTZeLglGpgFAiqCRLawsp/XG36 LZVJSbM2sLbv9b0vapiZ+0TT+e4VryQJP66mcrXrJ3gCJb7d4NCMvBSxbHPmyota57qlKtkX /7oT8uDa9nVKDGL/BGtl5Xbt/b5/s+jpjOBtjf0yj9Y61Gd/Etl6gWffzgvCV/LUeEzPf9bQ zPTWWPHMb0bymerMXvkbSizFGYmGWsxFxYkAsrUtSOoCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBLMWRmVeSWpSXmKPExsVy+t9jQd3HukWRBsu/K1hsnLGe1eL6l+es FufPb2C3+Nhzj9Xi8q45bBYzzu9jsrh4ytXi8Jt2VosfZ7pZHDg93t9oZfe43NfL5LFpVSeb R9+WVYwenzfJBbBGudlkpCampBYppOYl56dk5qXbKoWGuOlaKCnkJeam2ipF6PqGBCkplCXm lAJ5RgZowME5wD1YSd8uwS1jybwpTAXTJStevNrB3sC4QbSLkZNDQsBEYubKm8wQtpjEhXvr 2boYuTiEBFYzShz7O4sFwvnFKLFt2hFWkCo2AUOJ3qN9jCC2iICsxK1jP9lAbGaBp4wS0w4V gNjCArESDdt3MYHYLAKqEjdn9YDV8Aq4SRyds5gFYpucxMljk8Fmcgq4S+z4fhksLgRUs+r4 MqYJjLwLGBlWMXKlFhTnpucWGxUYbmIEhvK2w1r+Oxh/nI0+xCjAwajEw2vAUhQpxJpYVlyZ e4hRgoNZSYT3nzpQiDclsbIqtSg/vqg0J7X4EKMp0CkTmaVEk/OBcZZXEm9oYmlkYmBmZmhk YGymJM47IfBLhJBAemJJanZqakFqEUwfEwenVANjz++zvM/rHqaxNcyty5pl9VXrYf758oBg Bin+m4nxLF8Me6s2msqlmO4/Gp0TfXPS7GzWdZlSe72uRFkcmbA5NZLhhEW1cLVQyozPa9WV /A8IR9ftef8x53fcux8XeV7VcJdMOWJTtOXYrLtHBRzb1iie23Hi5ORWw60sd813bZm5i9OP jVNEiaU4I9FQi7moOBEAZ5eW/nsCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170721163755epcas1p2bfa1025557002ae5f89309aecd64c411 X-Msg-Generator: CA X-Sender-IP: 182.195.42.79 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 101P X-CMS-RootMailID: 20170721163755epcas1p2bfa1025557002ae5f89309aecd64c411 X-RootMTR: 20170721163755epcas1p2bfa1025557002ae5f89309aecd64c411 References: <1500655004-29816-1-git-send-email-s.nawrocki@samsung.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CLK_SET_RATE_PARENT flag is added to the clocks between the EPLL and the audio subsystem clock controller so that the EPLL's output frequency can be set indirectly with clk_set_rate() on a leaf clock. That should be safe as EPLL is normally only used to generate clock for the audio subsystem. With this change we can avoid passing the EPPL clock to the ASoC machine driver. Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 5ae9364..2560196 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -537,8 +537,8 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), - MUX(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, - SRC_TOP7, 20, 2), + MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, + SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), @@ -547,8 +547,8 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), - MUX(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, - SRC_TOP9, 8, 1), + MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, + SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, SRC_TOP9, 16, 1), MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, @@ -591,7 +591,7 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", - SRC_MASK_TOP7, 20, 0, 0), + SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), }; static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { @@ -633,7 +633,7 @@ static void __init exynos5420_clk_sleep_init(void) {} static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", - SRC_MASK_TOP7, 20, 0, 0), + SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), }; static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { @@ -713,7 +713,8 @@ static void __init exynos5420_clk_sleep_init(void) {} MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), - MUX(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), + MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, + CLK_SET_RATE_PARENT, 0), MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),