From patchwork Thu Jul 27 11:10:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 9866635 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0651E6038C for ; Thu, 27 Jul 2017 11:13:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ECA9328758 for ; Thu, 27 Jul 2017 11:13:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E1A69287C8; Thu, 27 Jul 2017 11:13:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76B6328758 for ; Thu, 27 Jul 2017 11:13:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751647AbdG0LLF (ORCPT ); Thu, 27 Jul 2017 07:11:05 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58468 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751641AbdG0LLB (ORCPT ); Thu, 27 Jul 2017 07:11:01 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0A9BE609F7; Thu, 27 Jul 2017 11:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1501153861; bh=Ra1bnHseCtToV9kHC6Re6pYR9U8Z312o97TTOmZsJhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kIq53dQ7TKjzpenRcUMz+EEwfvmEB4YQiXzIBJ9yqw/Jh7nedr1ABqT5BwqyT4b0w D5COeoTuFi360au8VwaFDwB2KMCOushsgy44Eee6R7ncoTKTucGf4IycpoBoB+O3VP 5mmWH8nl5wMhyql6GB8tLBcCGszLQmrU1DbHtkXk= Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5EE9260867; Thu, 27 Jul 2017 11:10:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1501153860; bh=Ra1bnHseCtToV9kHC6Re6pYR9U8Z312o97TTOmZsJhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cGznuDGw619l2cNesi7Lyaq9SgycZ9AjpudeWeqfmXivU519Uvf0lOOgtL172OLm1 mJFlt7X7hKsIsdli4Cb7oSZOld0iNTh6QTkGX9Ha1kkpFcMHvtqBpdrQs2okZaqRt4 qysZU3UFupY834F9qopsGdjT6/clvKe88IaKnTQo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5EE9260867 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [RFC 06/12] Clk: qcom: support for dynamic updating the PLL Date: Thu, 27 Jul 2017 16:40:19 +0530 Message-Id: <1501153825-5181-7-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501153825-5181-1-git-send-email-absahu@codeaurora.org> References: <1501153825-5181-1-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the Alpha PLL’s support dynamic update in which the frequency can be changed dynamically without turning off the PLL. This dynamic update requires the following sequence 1. Write the desired values to pll_l_val and pll_alpha_val. 2. Toggle pll_latch_input from low to high. 3. Wait for pll_ack_latch to transition from low to high. The new L and alpha values have been latched. It make take some time for the PLL to fully settle with these new values. 4. Pull pll_latch_input low. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 62 +++++++++++++++++++++++++++++++++------- drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 52 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 3a7ec42..e38f4d2 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -31,7 +31,10 @@ # define PLL_VOTE_FSM_ENA BIT(20) # define PLL_FSM_ENA BIT(20) # define PLL_VOTE_FSM_RESET BIT(21) +# define PLL_UPDATE BIT(22) +# define PLL_UPDATE_BYPASS BIT(23) # define PLL_OFFLINE_ACK BIT(28) +# define ALPHA_PLL_ACK_LATCH BIT(29) # define PLL_ACTIVE_FLAG BIT(30) # define PLL_LOCK_DET BIT(31) @@ -122,6 +125,15 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, #define wait_for_pll_offline(pll) \ wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") +#define wait_for_pll_update(pll) \ + wait_for_pll(pll, PLL_UPDATE, 1, "update") + +#define wait_for_pll_update_ack_set(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") + +#define wait_for_pll_update_ack_clear(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { @@ -398,7 +410,8 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); const struct pll_vco *vco; - u32 l, alpha_width = pll_alpha_width(pll); + u32 l, mode, alpha_width = pll_alpha_width(pll); + int ret; u64 a; rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); @@ -410,22 +423,49 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, pll_l(pll), l); - if (alpha_width > ALPHA_BITWIDTH) { - a <<= (alpha_width - ALPHA_BITWIDTH); - regmap_update_bits(pll->clkr.regmap, pll_alpha_u(pll), - GENMASK(0, alpha_width - ALPHA_BITWIDTH - 1), - a >> ALPHA_BITWIDTH); - } + a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; + + regmap_write(pll->clkr.regmap, pll_alpha(pll), a); + regmap_write(pll->clkr.regmap, pll_alpha_u(pll), a >> 32); regmap_update_bits(pll->clkr.regmap, pll_alpha(pll), GENMASK(0, alpha_width - 1), a); regmap_update_bits(pll->clkr.regmap, pll_user_ctl(pll), - PLL_VCO_MASK << PLL_VCO_SHIFT, - vco->val << PLL_VCO_SHIFT); + PLL_ALPHA_EN, PLL_ALPHA_EN); + + if (!clk_hw_is_enabled(hw) || !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) + return 0; + + regmap_read(pll->clkr.regmap, pll_mode(pll), &mode); + regmap_update_bits(pll->clkr.regmap, pll_mode(pll), PLL_UPDATE, + PLL_UPDATE); + + /* Make sure PLL_UPDATE request goes through*/ + mb(); - regmap_update_bits(pll->clkr.regmap, pll_user_ctl(pll), PLL_ALPHA_EN, - PLL_ALPHA_EN); + /* + * PLL will latch the new L, Alpha and freq control word. + * PLL will respond by raising PLL_ACK_LATCH output when new programming + * has been latched in and PLL is being updated. When + * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared + * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. + */ + if (!(mode & PLL_UPDATE_BYPASS)) + return wait_for_pll_update(pll); + + ret = wait_for_pll_update_ack_set(pll); + if (ret) + return ret; + + regmap_update_bits(pll->clkr.regmap, pll_mode(pll), PLL_UPDATE, 0); + + /* Make sure PLL_UPDATE request goes through*/ + mb(); + + ret = wait_for_pll_update_ack_clear(pll); + if (ret) + return ret; return 0; } diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 51a61a0..6e40e09 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -54,6 +54,7 @@ struct clk_alpha_pll { #define SUPPORTS_16BIT_ALPHA BIT(1) #define SUPPORTS_FSM_MODE BIT(2) #define SUPPORTS_64BIT_CONFIG_CTL BIT(3) +#define SUPPORTS_DYNAMIC_UPDATE BIT(4) u8 flags; struct clk_regmap clkr;