From patchwork Tue Aug 8 18:24:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Sahu X-Patchwork-Id: 9888919 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9396B601EB for ; Tue, 8 Aug 2017 18:27:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 85CEF289AB for ; Tue, 8 Aug 2017 18:27:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7A7F5289E0; Tue, 8 Aug 2017 18:27:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27992289AB for ; Tue, 8 Aug 2017 18:27:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752607AbdHHSZE (ORCPT ); Tue, 8 Aug 2017 14:25:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37404 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752516AbdHHSZB (ORCPT ); Tue, 8 Aug 2017 14:25:01 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 26F36605A8; Tue, 8 Aug 2017 18:25:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1502216701; bh=5xGuxwgKJ4XzhGIok/y+g3UQcLB2rHyaWJdw89wwHl8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jtW5MppwRPm2PFe1cQ+idL2OJe3snY6G4f7hpNZuONUEXcz540T+/8co8rXSDzQte SmmxFrASt7SfLW1+PUdC78bNryPaUj8ppQhOEKmtlopTZKCtcZIG38Qsi3McCq2Qb1 gkErAK5CKlOhTYrg0aJMP3PjzOtbZ6QrEg3c5ur0= Received: from absahu-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: absahu@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BBC626044E; Tue, 8 Aug 2017 18:24:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1502216700; bh=5xGuxwgKJ4XzhGIok/y+g3UQcLB2rHyaWJdw89wwHl8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gOoOjOxQqtA7n0BMCi4ygpG8H1hl4sFKEHXoEsB8tFf4xStUV2qNSZTQu0mZs6Unw IY1L28xG9gJ1Y/7MlpYqKQ3fAkSzhhX+cwWiTA80X8CV2boshEJ2JrM131xLLUIq/8 mUpxuXBbbngSlEKlMXbToteSszNOv1rgJtCuvypA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BBC626044E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [RFC v2 09/12] clk: qcom: support for 2 bit PLL post divider Date: Tue, 8 Aug 2017 23:54:14 +0530 Message-Id: <1502216657-3342-10-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1502216657-3342-1-git-send-email-absahu@codeaurora.org> References: <1502216657-3342-1-git-send-email-absahu@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Current PLL driver only supports 4 bit PLL post divider so modified the PLL divider operations to support 2 bit PLL post divider. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index b491dbe..4725f80 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -39,7 +39,6 @@ # define PLL_LOCK_DET BIT(31) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK 0xf # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25) # define PLL_VCO_SHIFT 20 @@ -738,7 +737,7 @@ static long clk_alpha_huayra_pll_round_rate(struct clk_hw *hw, regmap_read(pll->clkr.regmap, pll_user_ctl(pll), &ctl); ctl >>= PLL_POST_DIV_SHIFT; - ctl &= PLL_POST_DIV_MASK; + ctl &= BIT(pll->width) - 1; return parent_rate >> fls(ctl); } @@ -752,13 +751,26 @@ static long clk_alpha_huayra_pll_round_rate(struct clk_hw *hw, { } }; +static const struct clk_div_table clk_alpha_2bit_div_table[] = { + { 0x0, 1 }, + { 0x1, 2 }, + { 0x3, 4 }, + { } +}; + static long clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + const struct clk_div_table *table; + + if (pll->width == 2) + table = clk_alpha_2bit_div_table; + else + table = clk_alpha_div_table; - return divider_round_rate(hw, rate, prate, clk_alpha_div_table, + return divider_round_rate(hw, rate, prate, table, pll->width, CLK_DIVIDER_POWER_OF_TWO); } @@ -772,7 +784,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; return regmap_update_bits(pll->clkr.regmap, pll_user_ctl(pll), - PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT, + (BIT(pll->width) - 1) << PLL_POST_DIV_SHIFT, div << PLL_POST_DIV_SHIFT); }