From patchwork Tue Aug 29 08:38:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Binbin Zhou X-Patchwork-Id: 9926901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C9F2C6022E for ; Tue, 29 Aug 2017 08:46:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B82DD28898 for ; Tue, 29 Aug 2017 08:46:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ACD812889D; Tue, 29 Aug 2017 08:46:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3382728898 for ; Tue, 29 Aug 2017 08:46:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751651AbdH2IqS (ORCPT ); Tue, 29 Aug 2017 04:46:18 -0400 Received: from smtpbg328.qq.com ([14.17.43.160]:34694 "EHLO smtpbg328.qq.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751743AbdH2IqR (ORCPT ); Tue, 29 Aug 2017 04:46:17 -0400 X-QQ-mid: bizesmtp5t1503995887tyyp52fld Received: from software.domain.org (unknown [222.92.8.142]) by esmtp4.qq.com (ESMTP) with id ; Tue, 29 Aug 2017 16:38:06 +0800 (CST) X-QQ-SSF: 01100000008000F0FKF1B00A0000000 X-QQ-FEAT: f0dVAzX4zgnX9yvQ/wuURaAWdjNcRQDHrquomBwMoThPl3x+1lamskgUcqW5V qMHcwqC3cDgrg5c+nM+9xMQ8v6gpvbrKDP6tG+ZxH4v1kbl6TFRn6cwE6yB9sy9PqxBJjcm K+hrX7zwUN8+tBqBzuWsHLEgccDM8b9491d2Iqwz/LzZjDvtTGcGvvXpAI6xPVk54mL/Yp8 1J9oOlXYF1OXlI49OgMs3E+kk7XBq+g9olUsnDPmyF0DjvicRn8VKl2WQ3ZdabHGfbRLzma l/YeEHGw07q7+CMUAZ58X2uoqbVU28/mp1yYv3NjRQBxpbA5bZjf4w3PM= X-QQ-GoodBg: 0 From: Binbin Zhou To: Ralf Baechle , James Hogan Cc: John Crispin , "Steven J . Hill" , Aurelien Jarno , Fuxin Zhang , Zhangjin Wu , Kelvin Cheung , Yang Ling , =?UTF-8?q?=E8=B0=A2=E8=87=B4=E9=82=A6?= , Stephen Boyd , Michael Turquette , linux-mips@linux-mips.org, linux-clk@vger.kernel.org, Binbin Zhou , HuaCai Chen Subject: [PATCH RESEND v8 8/9] clk: Loongson: Add Loongson-1A clock support Date: Tue, 29 Aug 2017 16:38:45 +0800 Message-Id: <1503995926-17125-9-git-send-email-zhoubb@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1503995926-17125-1-git-send-email-zhoubb@lemote.com> References: <1503995926-17125-1-git-send-email-zhoubb@lemote.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:lemote.com:qybgweb:qybgweb19 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds clock support to Loongson-1A SoC. Unfortunately, The Loongson-1A's PLL register is written only, so we just set it with a fixed value. Acked-by: Stephen Boyd Signed-off-by: Binbin Zhou Signed-off-by: HuaCai Chen Cc: Michael Turquette Cc: linux-clk@vger.kernel.org --- arch/mips/include/asm/mach-loongson32/regs-clk.h | 30 +++++++++- drivers/clk/loongson1/Makefile | 1 + drivers/clk/loongson1/clk-loongson1a.c | 73 ++++++++++++++++++++++++ 3 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/loongson1/clk-loongson1a.c diff --git a/arch/mips/include/asm/mach-loongson32/regs-clk.h b/arch/mips/include/asm/mach-loongson32/regs-clk.h index e5e8f11..d8278a4 100644 --- a/arch/mips/include/asm/mach-loongson32/regs-clk.h +++ b/arch/mips/include/asm/mach-loongson32/regs-clk.h @@ -18,7 +18,35 @@ #define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) #define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) -#if defined(CONFIG_LOONGSON1_LS1B) +#if defined(CONFIG_LOONGSON1_LS1A) +/* write only */ +#define CORE_PLL_CFG 0x1fe78030 +#define CPU_MUL GENMASK(2, 0) +#define CPU_CFG_EN BIT(3) +#define DDR_MUL GENMASK(6, 4) +#define DDR_CFG_EN BIT(7) +#define CPU_CFG_W_EN BIT(11) +#define DDR_CFG_W_EN BIT(15) + +#define VGA_PLL_CFG 0x1fd00410 +#define VGA_M GENMASK(7, 0) +#define VGA_N GENMASK(11, 8) +#define VGA_OD GENMASK(13, 12) +#define VGA_FRAC GENMASK(31, 14) + +#define LCD_PLL_CFG 0x1fd00410 +#define LCD_M GENMASK(7, 0) +#define LCD_N GENMASK(11, 8) +#define LCD_OD GENMASK(13, 12) +#define LCD_FRAC GENMASK(31, 14) + +#define GPU_PLL_CFG 0x1fd00414 +#define GPU_M GENMASK(7, 0) +#define GPU_N GENMASK(11, 8) +#define GPU_OD GENMASK(13, 12) +#define GPU_FRAC GENMASK(31, 14) + +#elif defined(CONFIG_LOONGSON1_LS1B) /* Clock PLL Divisor Register Bits */ #define DIV_DC_EN BIT(31) #define DIV_DC_RST BIT(30) diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefile index b7f6a16..da7b2dd 100644 --- a/drivers/clk/loongson1/Makefile +++ b/drivers/clk/loongson1/Makefile @@ -1,3 +1,4 @@ obj-y += clk.o +obj-$(CONFIG_LOONGSON1_LS1A) += clk-loongson1a.o obj-$(CONFIG_LOONGSON1_LS1B) += clk-loongson1b.o obj-$(CONFIG_LOONGSON1_LS1C) += clk-loongson1c.o diff --git a/drivers/clk/loongson1/clk-loongson1a.c b/drivers/clk/loongson1/clk-loongson1a.c new file mode 100644 index 0000000..680bf1b --- /dev/null +++ b/drivers/clk/loongson1/clk-loongson1a.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2012-2016 Binbin Zhou + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include + +#include +#include "clk.h" + +#define OSC (33 * 1000000) +#define DIV_APB 2 + +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* Workaround, loongson-1A pll register is written only */ + return OSC * 8; +} + +static const struct clk_ops ls1x_pll_clk_ops = { + .recalc_rate = ls1x_pll_recalc_rate, +}; + +void __init ls1x_clk_init(void) +{ + struct clk_hw *hw; + + hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); + clk_hw_register_clkdev(hw, "osc_clk", NULL); + + /* clock from 33 MHz OSC clk */ + hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk", + &ls1x_pll_clk_ops, 0); + clk_hw_register_clkdev(hw, "pll_clk", NULL); + + /* cpu clk */ + hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "pll_clk", + 0, 1, 1); + clk_hw_register_clkdev(hw, "cpu_clk", NULL); + + /* dc clk */ + hw = clk_hw_register_fixed_factor(NULL, "ddr_clk", "pll_clk", + 0, 1, 1); + clk_hw_register_clkdev(hw, "ddr_clk", NULL); + + /* ahb clk */ + hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "pll_clk", + 0, 1, 2); + clk_hw_register_clkdev(hw, "ahb_clk", NULL); + clk_hw_register_clkdev(hw, "ls1x-dma", NULL); + clk_hw_register_clkdev(hw, "stmmaceth", NULL); + + /* clock derived from AHB clk */ + /* APB clk is always half of the AHB clk */ + hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", + 0, 1, DIV_APB); + clk_hw_register_clkdev(hw, "apb_clk", NULL); + clk_hw_register_clkdev(hw, "ls1x-ac97", NULL); + clk_hw_register_clkdev(hw, "ls1x-i2c", NULL); + clk_hw_register_clkdev(hw, "ls1x-nand", NULL); + clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL); + clk_hw_register_clkdev(hw, "ls1x-spi", NULL); + clk_hw_register_clkdev(hw, "ls1x-wdt", NULL); + clk_hw_register_clkdev(hw, "serial8250", NULL); +}