From patchwork Wed Oct 18 11:00:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 10013369 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1126A602C8 for ; Wed, 18 Oct 2017 02:57:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 012BE289D1 for ; Wed, 18 Oct 2017 02:57:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E8AFB289D6; Wed, 18 Oct 2017 02:57:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76A39289D1 for ; Wed, 18 Oct 2017 02:57:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753740AbdJRC5e (ORCPT ); Tue, 17 Oct 2017 22:57:34 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:8494 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752607AbdJRC5d (ORCPT ); Tue, 17 Oct 2017 22:57:33 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJG66693; Wed, 18 Oct 2017 10:57:24 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 10:56:03 +0800 From: Jiancheng Xue To: , CC: , , , , , tianshuliang , Jiancheng Xue Subject: [PATCH 2/3] clk: hisilicon: add emmc sample and drive clock for hi3798cv200 SoC Date: Wed, 18 Oct 2017 07:00:28 -0400 Message-ID: <1508324429-6012-3-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> References: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59E6C315.006D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3d4d91a454f65dda5af82117e416fc17 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: tianshuliang Add emmc sample and emmc drive clock for Hi3798cv200 SoC Signed-off-by: tianshuliang Signed-off-by: Jiancheng Xue --- drivers/clk/hisilicon/crg-hi3798cv200.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index ed8bb5f..25d750c 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -83,6 +83,18 @@ static struct hisi_mux_clock hi3798cv200_mux_clks[] = { CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, }, }; +static u32 mmc_phase_reg[] = {0, 1, 2, 3, 4, 5, 6, 7}; +static u32 mmc_phase_val[] = {0, 45, 90, 135, 180, 225, 270, 315}; + +static struct hisi_phase_clock hi3798cv200_phase_clks[] = { + { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_val, + mmc_phase_reg, ARRAY_SIZE(mmc_phase_reg)}, + { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_val, + mmc_phase_reg, ARRAY_SIZE(mmc_phase_reg)}, +}; + static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { /* UART */ { HISTB_UART2_CLK, "clk_uart2", "75m", @@ -179,11 +191,18 @@ static struct hisi_clock_data *hi3798cv200_clk_register( if (ret) goto unregister_fixed_rate; + ret = hisi_clk_register_phase(&pdev->dev, + hi3798cv200_phase_clks, + ARRAY_SIZE(hi3798cv200_phase_clks), + clk_data); + if (ret) + goto unregister_mux; + ret = hisi_clk_register_gate(hi3798cv200_gate_clks, ARRAY_SIZE(hi3798cv200_gate_clks), clk_data); if (ret) - goto unregister_mux; + goto unregister_phase; ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data->clk_data); @@ -201,6 +220,10 @@ static struct hisi_clock_data *hi3798cv200_clk_register( hisi_clk_unregister_mux(hi3798cv200_mux_clks, ARRAY_SIZE(hi3798cv200_mux_clks), clk_data); +unregister_phase: + hisi_clk_unregister_phase(hi3798cv200_phase_clks, + ARRAY_SIZE(hi3798cv200_phase_clks), + clk_data); unregister_gate: hisi_clk_unregister_gate(hi3798cv200_gate_clks, ARRAY_SIZE(hi3798cv200_gate_clks),