[v2,15/34] clk: vc5: change vc5_dbl_round_rate() return logic

Commit Message

Bryan O'Donoghue Jan. 1, 2018, 7:34 p.m. UTC

This patch updates the round_rate() logic here to return zero instead of a
negative number on error.

In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.

Signed-off-by: Bryan O'Donoghue <[e-mail]>
Cc: Marek Vasut <[e-mail]>
Cc: Michael Turquette <[e-mail]>
Cc: Stephen Boyd <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Cc: Vladimir Barinov <[e-mail]>
Cc: Alexey Firago <[e-mail]>
---
 drivers/clk/clk-versaclock5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 9432122..733b402 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -294,7 +294,7 @@  static unsigned long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
 	if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
 		return rate;
 	else
-		return -EINVAL;
+		return 0;
 }
 
 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,