From patchwork Wed Jan 24 12:45:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10182445 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5016A602B7 for ; Wed, 24 Jan 2018 12:45:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4CAC3228C8 for ; Wed, 24 Jan 2018 12:45:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41DD627F8C; Wed, 24 Jan 2018 12:45:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BCA84228C8 for ; Wed, 24 Jan 2018 12:45:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933386AbeAXMpw (ORCPT ); Wed, 24 Jan 2018 07:45:52 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13128 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933681AbeAXMpt (ORCPT ); Wed, 24 Jan 2018 07:45:49 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 24 Jan 2018 04:45:33 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 24 Jan 2018 04:45:49 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 24 Jan 2018 04:45:49 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 24 Jan 2018 12:45:48 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 24 Jan 2018 12:45:44 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 828D1F81123; Wed, 24 Jan 2018 14:45:41 +0200 (EET) From: Peter De Schrijver To: , , , CC: Peter De Schrijver Subject: [PATCH v2 6/6] cpufreq: tegra124-cpufreq: extend to support Tegra210 Date: Wed, 24 Jan 2018 14:45:38 +0200 Message-ID: <1516797938-32044-8-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516797938-32044-1-git-send-email-pdeschrijver@nvidia.com> References: <1516797938-32044-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra210 has a very similar CPU clocking scheme than Tegra124. So add support in this driver. Also allow for the case where the CPU voltage is controlled directly by the DFLL rather than by a separate regulator object. Signed-off-by: Peter De Schrijver --- drivers/cpufreq/tegra124-cpufreq.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 4353025..d631dc4 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -64,7 +64,8 @@ static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv) { clk_set_parent(priv->cpu_clk, priv->pllp_clk); clk_disable_unprepare(priv->dfll_clk); - regulator_sync_voltage(priv->vdd_cpu_reg); + if (priv->vdd_cpu_reg) + regulator_sync_voltage(priv->vdd_cpu_reg); clk_set_parent(priv->cpu_clk, priv->pllx_clk); } @@ -89,10 +90,8 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) return -ENODEV; priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu"); - if (IS_ERR(priv->vdd_cpu_reg)) { - ret = PTR_ERR(priv->vdd_cpu_reg); - goto out_put_np; - } + if (IS_ERR(priv->vdd_cpu_reg)) + priv->vdd_cpu_reg = NULL; priv->cpu_clk = of_clk_get_by_name(np, "cpu_g"); if (IS_ERR(priv->cpu_clk)) { @@ -148,7 +147,6 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) clk_put(priv->cpu_clk); out_put_vdd_cpu_reg: regulator_put(priv->vdd_cpu_reg); -out_put_np: of_node_put(np); return ret; @@ -181,7 +179,8 @@ static int __init tegra_cpufreq_init(void) int ret; struct platform_device *pdev; - if (!of_machine_is_compatible("nvidia,tegra124")) + if (!(of_machine_is_compatible("nvidia,tegra124") + || of_machine_is_compatible("nvidia,tegra210"))) return -ENODEV; /*