From patchwork Tue Jan 30 23:23:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Giulio Benetti X-Patchwork-Id: 10192909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 91C13601A0 for ; Tue, 30 Jan 2018 23:34:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8696D27FA8 for ; Tue, 30 Jan 2018 23:34:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 79606280B0; Tue, 30 Jan 2018 23:34:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B52827FA8 for ; Tue, 30 Jan 2018 23:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752763AbeA3XeK (ORCPT ); Tue, 30 Jan 2018 18:34:10 -0500 Received: from mail.micronovasrl.com ([212.103.203.10]:58644 "EHLO mail.micronovasrl.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752755AbeA3XeK (ORCPT ); Tue, 30 Jan 2018 18:34:10 -0500 X-Greylist: delayed 555 seconds by postgrey-1.27 at vger.kernel.org; Tue, 30 Jan 2018 18:34:09 EST Received: from mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) by mail.micronovasrl.com (Postfix) with ESMTP id D4DEEB00D6D for ; Wed, 31 Jan 2018 00:24:53 +0100 (CET) Authentication-Results: mail.micronovasrl.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=micronovasrl.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=micronovasrl.com; h=x-mailer:message-id:date:date:subject:subject:to:from:from; s=dkim; t=1517354693; x=1518218694; bh=6wjI30ppPkJAPZOyHGk/Gzp7 OaO/6OGHbvaQhUM93Nc=; b=jJhNm5I910KpJuuxeQK4sU6+f6oc4gP/iFJeqCek bgQxhWVAm94t4MSdB7sdnPjYXpLZI6vmGcIY13TyJFmkmh8EvhR7pZMYi/KEkcqe DH4Ovx6v/VM0c1CW1l0Ih53pvSarwrd0nXHw7lm/6tbq/r8cdgAh/WvzcvoPol7x 9/E= X-Virus-Scanned: Debian amavisd-new at mail.micronovasrl.com Received: from mail.micronovasrl.com ([127.0.0.1]) by mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id UEgWiBp_Eo0w for ; Wed, 31 Jan 2018 00:24:53 +0100 (CET) Received: from localhost.localdomain (unknown [192.168.123.47]) by mail.micronovasrl.com (Postfix) with ESMTPSA id 90831B001B3; Wed, 31 Jan 2018 00:24:52 +0100 (CET) From: Giulio Benetti To: Maxime Ripard Cc: Chen-Yu Tsai , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Giulio Benetti Subject: [PATCH] clk: sunxi-ng: ccu-sun4i-a10: Fix mali changing dclk frequency Date: Wed, 31 Jan 2018 00:23:59 +0100 Message-Id: <1517354639-92978-1-git-send-email-giulio.benetti@micronovasrl.com> X-Mailer: git-send-email 2.7.4 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When mali.ko is inserted, it set default clocks and call all parent clocks to stay into range, causing pll-video0 to change and subsequently to change dclk to wrong frequencies. "gpu" clock has lot of parent plls inside driver, but on sun7i pll8-gpu does not depend on pll-video0, pll-ve, pll-video1. It only depends on 24Mhz main clock. Remove all pll parents from gpu_parents_sun7i except "pll-gpu". Signed-off-by: Giulio Benetti --- drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c index ffa5dac..49726a6 100644 --- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c @@ -790,9 +790,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i, 0x154, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); -static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve", - "pll-ddr-other", "pll-video1", - "pll-gpu" }; +static const char *const gpu_parents_sun7i[] = { "pll-gpu" }; static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 }; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu", gpu_parents_sun7i, gpu_table_sun7i,