From patchwork Fri Feb 9 09:48:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 10208683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9783860247 for ; Fri, 9 Feb 2018 09:49:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6B850201CB for ; Fri, 9 Feb 2018 09:49:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5FE63295AF; Fri, 9 Feb 2018 09:49:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 97F5F201CB for ; Fri, 9 Feb 2018 09:49:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751053AbeBIJsf (ORCPT ); Fri, 9 Feb 2018 04:48:35 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:36627 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750924AbeBIJsc (ORCPT ); Fri, 9 Feb 2018 04:48:32 -0500 Received: by mail-pg0-f68.google.com with SMTP id j9so2207167pgv.3; Fri, 09 Feb 2018 01:48:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I528KVET1FWi+s982KmJLzIYfzuLIMLEsdcFwnVDx1M=; b=fCA1zsNwC8rSlsOTnzFSHr72j753ZTIqs6PWaVi+Az++LKY3Cqupav1zKcQgGl7tk+ fSEkGO3CHggtTN1usApbvtKqrZ39jm88JpnX8HX7D5D51oKi0nqM9Zq8IZQkuin2oO3e OvXcIdUrI3mshUruxXeZyGO+U8e9K2tfMJBztd4qV+qIIdPG6XaLp3dpn6FyzmYOyC3/ 5lYS6PBbUrk8xPLk+rBa3sjRq0xJz9rErUjUzgABGuenuoRhaI6VRu0B4TacdaATpUEC oR9Xxab7N8Qr42/t4z+3u9C5Iw6Pi5AWHkuEPar5yNQZxPR8NejWv8uyrseM1vIFumpZ 6sfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I528KVET1FWi+s982KmJLzIYfzuLIMLEsdcFwnVDx1M=; b=DQdnzHOdaLwxgFEM8upXAsUR2giB9dZZfmTc3J/csVVpdS6Vdbef0+644GAKR5+39y YYopCmDzs9cEPqDDxrrlc1uUhObHbNNVvujEtNm61e0ZkxrxcxJhqUBIFwlw3msvTnwY Hh/y2tATOxugRK+6m4CBFmLYK3WcMccAEsKIhdEOvggJp+xzosk+bxda7U7rdkmb1YSd 4AeT2Z27OJt/0tA7vmlp7nsWW3BZhyRJwaHDBH1Ae/bta1ZWdvNWFiANYPk2sh8MzSBI /dC1tEXw1GSC/4lIOczHTGxXhoX7TYTHu2fcwE6Xyda0MfpZx24T/rnRwhPBoHGUtI0y pf2Q== X-Gm-Message-State: APf1xPD9cY6Wl95zwPqX/Sp2PDd9sEpmfuy+p9ncPAzk33kNRRjzmbDb eZTiOTJhHbu7gde8Y+OmMSM= X-Google-Smtp-Source: AH8x2277T4nZlQ1+fPDsNoXhAyhrv/rBvYq4kizPgNVslo9WI0i+aNrXndbT4gmrIAE+oLvAMwiW7A== X-Received: by 10.99.175.76 with SMTP id s12mr1910975pgo.240.1518169712026; Fri, 09 Feb 2018 01:48:32 -0800 (PST) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id b8sm5745205pfl.129.2018.02.09.01.48.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 01:48:31 -0800 (PST) From: Chunyan Zhang To: Stephen Boyd , Rob Herring Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: [PATCH 2/2] clk: sprd: add RTC gate for SC9860 Date: Fri, 9 Feb 2018 17:48:11 +0800 Message-Id: <1518169691-14870-2-git-send-email-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518169691-14870-1-git-send-email-zhang.lyra@gmail.com> References: <1518169691-14870-1-git-send-email-zhang.lyra@gmail.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chunyan Zhang Add a few gate clocks which are used for gating RTC for some devices on AON area of SC9860. Signed-off-by: Chunyan Zhang --- drivers/clk/sprd/sc9860-clk.c | 76 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c index ed5c027..9980ab5 100644 --- a/drivers/clk/sprd/sc9860-clk.c +++ b/drivers/clk/sprd/sc9860-clk.c @@ -959,6 +959,44 @@ static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c, 0x1000, BIT(6), 0, 0); static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c, 0x1000, BIT(9), 0, 0); +static SPRD_SC_GATE_CLK(arch_rtc_eb, "arch-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(kpb_rtc_eb, "kpb-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(aon_syst_rtc_eb, "aon-syst-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(ap_syst_rtc_eb, "ap-syst-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10, + 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(dcxo_tmr_rtc_eb, "dcxo-tmr-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(bb_cal_rtc_eb, "bb-cal-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(avs_big_rtc_eb, "avs-big-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(avs_lit_rtc_eb, "avs-lit-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(avs_gpu0_rtc_eb, "avs-gpu0-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(avs_gpu1_rtc_eb, "avs-gpu1-rtc-eb", "aon-apb", 0x10, + 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(gpu_ts_eb, "gpu-ts-eb", "aon-apb", 0x10, + 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); +static SPRD_SC_GATE_CLK(rtcdv10_eb, "rtcdv10-eb", "aon-apb", 0x10, + 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); static struct sprd_clk_common *sc9860_aon_gate[] = { /* address base is 0x402e0000 */ @@ -1030,6 +1068,25 @@ static struct sprd_clk_common *sc9860_aon_gate[] = { &sdio1_2x_en.common, &sdio2_2x_en.common, &emmc_2x_en.common, + &arch_rtc_eb.common, + &kpb_rtc_eb.common, + &aon_syst_rtc_eb.common, + &ap_syst_rtc_eb.common, + &aon_tmr_rtc_eb.common, + &ap_tmr0_rtc_eb.common, + &eic_rtc_eb.common, + &eic_rtcdv5_eb.common, + &ap_wdg_rtc_eb.common, + &ap_tmr1_rtc_eb.common, + &ap_tmr2_rtc_eb.common, + &dcxo_tmr_rtc_eb.common, + &bb_cal_rtc_eb.common, + &avs_big_rtc_eb.common, + &avs_lit_rtc_eb.common, + &avs_gpu0_rtc_eb.common, + &avs_gpu1_rtc_eb.common, + &gpu_ts_eb.common, + &rtcdv10_eb.common, }; static struct clk_hw_onecell_data sc9860_aon_gate_hws = { @@ -1102,6 +1159,25 @@ static struct clk_hw_onecell_data sc9860_aon_gate_hws = { [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw, [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw, [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw, + [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw, + [CLK_KPB_RTC_EB] = &kpb_rtc_eb.common.hw, + [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw, + [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw, + [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw, + [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw, + [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw, + [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw, + [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw, + [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw, + [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw, + [CLK_DCXO_TMR_RTC_EB] = &dcxo_tmr_rtc_eb.common.hw, + [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw, + [CLK_AVS_BIG_RTC_EB] = &avs_big_rtc_eb.common.hw, + [CLK_AVS_LIT_RTC_EB] = &avs_lit_rtc_eb.common.hw, + [CLK_AVS_GPU0_RTC_EB] = &avs_gpu0_rtc_eb.common.hw, + [CLK_AVS_GPU1_RTC_EB] = &avs_gpu1_rtc_eb.common.hw, + [CLK_GPU_TS_EB] = &gpu_ts_eb.common.hw, + [CLK_RTCDV10_EB] = &rtcdv10_eb.common.hw, }, .num = CLK_AON_GATE_NUM, };