From patchwork Fri Mar 9 01:51:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 10269525 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1A1016037E for ; Fri, 9 Mar 2018 01:57:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0443729C46 for ; Fri, 9 Mar 2018 01:57:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EC3BC29C49; Fri, 9 Mar 2018 01:57:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_WEB autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 900C029C46 for ; Fri, 9 Mar 2018 01:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751173AbeCIB5U (ORCPT ); Thu, 8 Mar 2018 20:57:20 -0500 Received: from lucky1.263xmail.com ([211.157.147.135]:38696 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751113AbeCIB5T (ORCPT ); Thu, 8 Mar 2018 20:57:19 -0500 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.172]) by lucky1.263xmail.com (Postfix) with ESMTP id 375406B64; Fri, 9 Mar 2018 09:57:12 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id DAD6D3B7; Fri, 9 Mar 2018 09:57:09 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <697dfb52624ab8f0ca5052a6822eb034> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 20631GZJ68K; Fri, 09 Mar 2018 09:57:11 +0800 (CST) From: Shawn Lin To: Heiko Stuebner , Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Shawn Lin Subject: [PATCH] clk: rockchip: Restore the clock phase after the rate was changed Date: Fri, 9 Mar 2018 09:51:03 +0800 Message-Id: <1520560263-123065-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are many factors affecting the clock phase, including clock rate, temperature, logic voltage and silicon process, etc. But clock rate is the most significant one here, and the driver should be aware of the change of the clock rate. As mmc controller need a fixed phase after tuning was completed, at least before explicitly doing re-tune, so this patch try to restore the clock phase by monitoring the event of rate change. Signed-off-by: Shawn Lin --- drivers/clk/rockchip/clk-mmc-phase.c | 39 +++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c index fe7d9ed..dc4c227 100644 --- a/drivers/clk/rockchip/clk-mmc-phase.c +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -25,6 +25,8 @@ struct rockchip_mmc_clock { void __iomem *reg; int id; int shift; + int cached_phase; + struct notifier_block clk_rate_change_nb; }; #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw) @@ -162,6 +164,29 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) .set_phase = rockchip_mmc_set_phase, }; +#define to_rockchip_mmc_clock(x) \ + container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb) +static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb); + + /* + * rockchip_mmc_clk is mostly used by mmc controllers to sample + * the intput data, which expects the fixed phase after the tuning + * process. However if the clock rate is changed, the phase is stale + * and may break the data sampling. So here we try to restore the phase + * for that case. + */ + if (event == PRE_RATE_CHANGE) + mmc_clock->cached_phase = + rockchip_mmc_get_phase(&mmc_clock->hw); + else if (event == POST_RATE_CHANGE) + rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase); + + return NOTIFY_DONE; +} + struct clk *rockchip_clk_register_mmc(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *reg, int shift) @@ -169,6 +194,7 @@ struct clk *rockchip_clk_register_mmc(const char *name, struct clk_init_data init; struct rockchip_mmc_clock *mmc_clock; struct clk *clk; + int ret; mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL); if (!mmc_clock) @@ -186,7 +212,18 @@ struct clk *rockchip_clk_register_mmc(const char *name, clk = clk_register(NULL, &mmc_clock->hw); if (IS_ERR(clk)) - kfree(mmc_clock); + goto err_register; + mmc_clock->clk_rate_change_nb.notifier_call = + &rockchip_mmc_clk_rate_notify; + ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb); + if (ret) + goto err_notifier; + + return clk; +err_notifier: + clk_unregister(clk); +err_register: + kfree(mmc_clock); return clk; }