From patchwork Fri Apr 20 12:27:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 10352545 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B6D2F60365 for ; Fri, 20 Apr 2018 12:28:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A7C57286BF for ; Fri, 20 Apr 2018 12:28:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9BFD128700; Fri, 20 Apr 2018 12:28:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CC0F286BE for ; Fri, 20 Apr 2018 12:28:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754607AbeDTM2Q (ORCPT ); Fri, 20 Apr 2018 08:28:16 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:62631 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754705AbeDTM2L (ORCPT ); Fri, 20 Apr 2018 08:28:11 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie3.idc.renesas.com with ESMTP; 20 Apr 2018 21:28:07 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 0B3569B2FC; Fri, 20 Apr 2018 21:28:08 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.49,301,1520866800"; d="scan'208";a="277384810" Received: from mail-ty1jpn01lp0180.outbound.protection.outlook.com (HELO JPN01-TY1-obe.outbound.protection.outlook.com) ([23.103.139.180]) by relmlii1.idc.renesas.com with ESMTP/TLS/AES256-GCM-SHA384; 20 Apr 2018 21:28:07 +0900 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=renesasgroup.onmicrosoft.com; s=selector1-renesas-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=YhM3MAwpHXWvR9L8/nasQ6pJvXkIHHru39HSlLWhZSs=; b=DPxKOPwvXbquXxBL7Tts47Jl/FD+Dsd2TDle9DVWujIwMPkjzlffmW83BgaWulrRMZOGPYq256DoPeGQNr/UP9Je7WDXqkekJhtAa2mSAj+cJ7Op+CsDLaXlsKFYdTcQTbP6oeqXtrThAKv8dWdsDCTSQQdNmYxsM1cUQ6RB818= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=<>; Received: from localhost.localdomain (211.11.155.138) by TY1PR06MB0992.apcprd06.prod.outlook.com (2a01:111:e400:59f2::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.696.14; Fri, 20 Apr 2018 12:28:05 +0000 From: Yoshihiro Shimoda To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, geert+renesas@glider.be, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 2/2] clk: renesas: cpg-mssr: Add support for R-Car E3 Date: Fri, 20 Apr 2018 21:27:44 +0900 Message-Id: <1524227264-24896-3-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1524227264-24896-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1524227264-24896-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Originating-IP: [211.11.155.138] X-ClientProxiedBy: KAXPR01CA0041.jpnprd01.prod.outlook.com (2603:1096:402:1a::27) To TY1PR06MB0992.apcprd06.prod.outlook.com (2a01:111:e400:59f2::26) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(4534165)(4627221)(201703031133081)(8559017)(5600026)(2017052603328)(7153060)(7193020); SRVR:TY1PR06MB0992; X-Microsoft-Exchange-Diagnostics: 1; TY1PR06MB0992; 3:sqV0QGdFdTiJGXjPks3OX/68sqf2QXD7Q0uVCPVmejJfSvDXSONECxWcHk1eBJ2xqFwvcPzCvW68iJoJh4hQHErAn3OgjZNyks18ZIwlFqlBchhHEe1QA5XqpEP3ZixRZCsRtlBW88+K2QtNksMw3Tu+RySMe1G2cRt+FlrOpzN9/wFO98PEBA5BiPPmm/u6uYJn7KGrGa1Te+Dlc3QwOKUBM32r+TbX+Y74iTyFKDsvRwydgFSVau7InYqq58an; 25:q22f3f0z8N4K4FJpDFP6JaFQq1HULYIPgpfQCYxbEK0D7gvzkeuOpTJT9X6fyK8fANWi8aOs0WeFL2DXDCu8HWKKn0Pw97unKBBW88ARhHSc6z3RqUz3rLwjgFWLshuwztaJFTW8B3gQhy25FcYBCLl90OkrCoLnxj7qbAsOLLTMJGlUYipa+ENs5eUAUSTkbeWe5OfXxFVp+7ZEf5YFnvnXRd1MSqGXOI0tFQEFMI55aeMflPgXD47Zx9ECqHRkbKuMLhC5ITt5XdzOYefeh0bZChPgAPrKKSh0HHsCWPQr/8/RykO7dkXCW/eBgzG2aleYMyRaWRYtk9C5zkyFMw==; 31:WPTxfygkLflOA7N032CoADPk28GEc0d6R5K+s/3i7kk0vjVzhDTYDeh5PE8uQTS+b49FdRkDnPKyfiS1zNidfzN35GK1rVWNc7hk2UCe8nF/g0+lBe/TwFGVte/qUxg4uFugINBlBzX7Y7rtoTDuWNQ/16HLu56YKZRcnhLgJUdqvEp0siP18Lay2gwvj1FMYDjytzhMbvCtTVUnyUvpsxo3IFSgwkC+ieE9Wy3yuKk= X-MS-TrafficTypeDiagnostic: TY1PR06MB0992: X-Microsoft-Exchange-Diagnostics: 1; TY1PR06MB0992; 20:uOQKREJzJwZzZC3EygHRguu6Ml/SMA65/NffEyzH4dPGXQhuTop+3lkA0pEC+aRr4ydJSQJBIdornu+h0ZkJ2neVdwSyxSim+jbKy8N3KxqAHAOhVGWlHnTf7k/TQ8E66Y413xk3PhM3uE71I3EFstVk6XnnyUFtyiC2V28yCPukieAXEIDds70hZffgvVSFFElwcZuSTHYa+JFOHL0FHhQVkYxYrs0vyewRdoGCchXWCLAtfrhpQ2sERGorUt+3Ro0TLP1gi8xmgXLrImdNlgojzRqwk55dDDLaEdOPu0WrL6Of06P/HN/nFH4oQdj+6iHoYdxUnz3pRYS9fPT8rkIaJwju5hajRyK+hZbWFlqX6Ug4/+mYCaI30AVIrYXcNlvr+6qrH8v2PHw8l90rCdSP1/X89UyoWf/C1EfvtIkyXe/PU5WkWhvMYi7ZL+y4a9UryHMSSQh2YSEcXeyaLEJ5WXcsXVElYtWbDWysoQweXQCofApvuFtFNWo6oZvP; 4:sUlfNt2ysjajcDBP8UFGZ+3WvS4MH37a1+ZL8HAaiFBTQSJ3FDozK3k5478Nvv/jW9lQBSLzZrM2AKcYz5KiVhoSPtPEhQgs2KUoa0CsejpnN4x6Q0XjXmfc68yJfJ2nPAmuiXj/cjyvr7R1gla+YuzTjW8jHUPlvbJdq+/qWgsbkn67xHcRo9VfSj3+/5IOBPjBk8H+qkBzvK8ijgSeg+GJCL1oybBk76XAFxnKjeIFm2zpsBQzVM7vErgtDmC44uRLVoWsXKe7GP87z1P4SQ== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(3231232)(944501393)(52105095)(6055026)(6041310)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061750153)(20161123558120)(20161123562045)(20161123560045)(6072148)(201708071742011); SRVR:TY1PR06MB0992; BCL:0; PCL:0; RULEID:; SRVR:TY1PR06MB0992; X-Forefront-PRVS: 0648FCFFA8 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6069001)(396003)(376002)(39860400002)(346002)(39380400002)(366004)(50226002)(16586007)(66066001)(6506007)(316002)(386003)(76176011)(59450400001)(498600001)(51416003)(52116002)(47776003)(8936002)(81166006)(6512007)(78352004)(8676002)(3846002)(4326008)(6486002)(6116002)(25786009)(446003)(7736002)(2616005)(305945005)(11346002)(6666003)(50466002)(42882007)(5660300001)(48376002)(36756003)(16526019)(53936002)(26005)(2906002)(107886003)(575784001)(476003)(956004)(3720700003); DIR:OUT; SFP:1102; SCL:1; SRVR:TY1PR06MB0992; H:localhost.localdomain; FPR:; SPF:None; LANG:en; MLV:ovrnspm; PTR:InfoNoRecords; Received-SPF: None (protection.outlook.com: localhost.localdomain does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; TY1PR06MB0992; 23:ebOWdFjSK82Kv2ZK8ZhkADzPyJxzupEaiBLT1sUw+?= =?us-ascii?Q?h+cKrPxhZublB/HdDAN3+yYvSI6xrI+F6Wzc2Zb8cJP/mpr6Rrm6rgJf3V2f?= =?us-ascii?Q?oi/hIAPWNQlw51aUArxS5CB6Ycf2DrFOR4d/lHj99zT0jBEv2WqrGxwMQ1cu?= =?us-ascii?Q?kr29nOfZl5RD2HE+djC7wuuZbr+aSEAeE5DCA3bTzf5YOBD8IpboDVWWb2M1?= =?us-ascii?Q?BtMZ/0fLBhtkY9hXEZrGN6b6VeAfYP37nH4GaysQJW6YeXVh+823brLSBr0t?= =?us-ascii?Q?6NrF9hSvKDtcVnzIwqNHmB4BeiXf5t3USIuBVh0R3mekcngrNDwcqdC6VrZz?= =?us-ascii?Q?nfFLm1iZ/MS6IyhAE6Z9PVEo8KRZLrv6DN7n3o3WMQ+bYLxEm3y4HrQUnrKi?= =?us-ascii?Q?jIEdq6UB3wnGUbbsKUsAvuOSvAdqdei3Pfl5hpS+iFOOvS3sX+Fhfa2VE9oW?= =?us-ascii?Q?kaXuT3gDEuzsmCd5BDSs0n23ID0Em4aGdE8bEuUeBDevKkC1rp5PkbK+52Pt?= =?us-ascii?Q?QuDoO++Y9jwOwXoLqfgWjA3IzjAhj5lFcwr9wvQYGsVk+dF9vM2TUNQMF2+B?= =?us-ascii?Q?Nc3DNKwLn1W+nqquNTe8zgNZsvEfTU/D9Ino6d85PExV6tdVUIjlcjRYAl6O?= =?us-ascii?Q?1/uJTed3z8QE6wzNIwoCi9VGqG9lzQr4vsKNkdZ7en6L+HZaH1TeMtHpoD+k?= =?us-ascii?Q?M6k9vRN/R5DDMpmRT1dps5PxJ1NtP6ou5t0LUVxMSFhy0fdtL/l8Sw+QWFby?= =?us-ascii?Q?HTrl/rc3rL3KL48k22dynSSgVY5+vpZ9ME5IRXNpEFHzqV/AayQmXWMyzruN?= =?us-ascii?Q?Jo80e33EGRJbrOpk5tpmQPAFR0P+IAV4Pym4ca8ECgBh5EQzS5sMvW1e9Z5Z?= =?us-ascii?Q?qc61IVy0Ey3WKcpDiF6KTcErOTBe5dqoQ4EOS+Ouh72o225V7dB1oN/c8w+t?= =?us-ascii?Q?0JkOA8QKIAucQmaJpfB4EJQDFzFx/r9uCRuN+tTZVaty5+CGt/8j5GFMUeh2?= =?us-ascii?Q?CkOPERRwhev8APXIsZ4DSyj35LHy3jGpQLXQXTV438i186kWA2O1QIOuhKAn?= =?us-ascii?Q?CMO+lP/AK58q0B4QeYfGZSPLZzwKBF7o4lKFmLyW0zKT/MLp/S0APasO84nV?= =?us-ascii?Q?stz5CbxcRg=3D?= X-Microsoft-Antispam-Message-Info: gZ3rxFK2BHjwr+rfrfMaiH3b5GlojVzD0eqXXSJSfZ12jo+dGhsgyYpHTd2uZeonXyM2ks0w78n0VDPgqdnlDrs6+Vd64wu60rRe3t3khPgKHXj66aYTaV4+0XV/FQowcdAI5ZXBO/Y1MxTrwUg8EuFyCB7Snoc20+W56ABORx1S0SPpcDxhfvAszKD4w2E/ X-Microsoft-Exchange-Diagnostics: 1; TY1PR06MB0992; 6:ny2FT8+sTlMMj3rIgs0tKtKu4NadvU6k/nSA65BQ0+irR40UJek1qSFNuZt9wIQKSL94pheg3jAh1y+sbGjzl3ZL3/qchUuDYuTiB+QY5HVfJiJfNHxq4PRN/htpjd8Ws6u1TjiOvcdPcohWAmd4L1ylLVhthbK6am2YbIgNi5G5bd8pxD/8WX7caQVfcUS9iRn0veQIfUUJWgwV8KobWxfdPAZVEBVi0idIjK/UqtP3rKkrFK4+sW5qWnRF0U2ChG20d0Noz3hdqeY+EhSbX4kZQa1QNXUqj42rrWzjuUWyJa+N+N9ttmRBEEFIaWXoWwUT2GsBGaPUYEwbr5eSRXOCFk5WNLIvMxR7rUWTMgV2VQNK3qwdFzXK8PylSyi9Lu+ZSPu2WkEwf29JxS6ztfd6k+Jg8lnEErpv/aK/JFTvtSFm0MZL5lEEiQbeBvRXSZIMkDomcB5i3Kl0eRqf0Q==; 5:vGulqoE/Gfm8Wvt3elQ2TGvO3rvQhJphdggAH7ZF1qbfP+0SU2asqTF6w/fpzCOhtO8YKo/zYXCMZ7YbHtMlfpReDIG/k3+OyLQMkHTWvrolRT7VOhnvwj3HUyaw3txVWoilk0Ml5X5wAl1wOriGGjvEihWpfD8gdTWxpiBYU80=; 24:P07i3RcNJ+dcc4hyEqABV0GTu5OHvi14VWOQaKz1iLwr8UJvu5BrI6upWkHdOUCDSPKLAClF2tVLfnaspz2UXAstEQavPKdDkrRRq9bgdXA= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; TY1PR06MB0992; 7:g0cThiBqwbkoLVbBw+Nn/70/iXlrrTb9bDwrIMNN+czsPkULPMz7AJI1ZNd3raQbiTSikW+qZyJy++wUxao4uEh4ZycdilTUqEzrp7Jgm//c8Lk8xhq48SX7XBmErAQBKvZ3ETXQI1C0jfP8XYC928qOroYHzQLm1cDBtfHc1BSzxLqbhlUTJEHiKNLc8VdkMwObREtTv4eywMDsG9i2JozBbCkHiHRoS7MjaQUo3psOJOrXliqV6AevD21A6USf; 20:xuF2SuaMAq3KC2GF7XQna9ezf8rghmu2kMSg85NUeX4RHoopK/vYMGTwk3Gf2jMg1HT8ltp5EudYt19xkOb8JR14DH1MulO18kdvo6iafR+YwJMOWV2glJCFGGVmJsfqJUODAUAn+pbb0Z5egzVRuxb10Y8j2ZXsKCFTxOyA0+M= X-MS-Office365-Filtering-Correlation-Id: 36cec26f-6216-474a-a71f-08d5a6ba2ab1 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2018 12:28:05.2113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36cec26f-6216-474a-a71f-08d5a6ba2ab1 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY1PR06MB0992 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Initial support for R-Car E3 (r8a77990), including core and module clocks. Based on the Table 8.2g of "R-Car Series, 3rd Generation User's Manual: Hardware ((Rev. 0.80, Oct 31, 2017) with Manual Errata on Feb. 28, 2018". Inspried by patches by Takeshi Kihara in the BSP. Signed-off-by: Yoshihiro Shimoda --- .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 3 +- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a77990-cpg-mssr.c | 289 +++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 6 files changed, 304 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r8a77990-cpg-mssr.c diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index c3473df..db542ab 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -26,6 +26,7 @@ Required Properties: - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) + - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3) - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) - reg: Base address and length of the memory resource used by the CPG/MSSR @@ -36,7 +37,7 @@ Required Properties: - clock-names: List of external parent clock names. Valid names are: - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, - r8a77980, r8a77995) + r8a77980, r8a77990, r8a77995) - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, r8a7794) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index f32896fa..f9ba71311 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -19,6 +19,7 @@ config CLK_RENESAS select CLK_R8A77965 if ARCH_R8A77965 select CLK_R8A77970 if ARCH_R8A77970 select CLK_R8A77980 if ARCH_R8A77980 + select CLK_R8A77990 if ARCH_R8A77990 select CLK_R8A77995 if ARCH_R8A77995 select CLK_SH73A0 if ARCH_SH73A0 @@ -116,6 +117,10 @@ config CLK_R8A77980 bool "R-Car V3H clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG +config CLK_R8A77990 + bool "R-Car E3 clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A77995 bool "R-Car D3 clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index a4edea9..fe5bac9 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c new file mode 100644 index 0000000..bf439e2 --- /dev/null +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * r8a77990 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2018 Renesas Electronics Corp. + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77990_CLK_CPEX, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL3, + CLK_PLL0D4, + CLK_PLL0D6, + CLK_PLL0D8, + CLK_PLL0D20, + CLK_PLL0D24, + CLK_PLL1D2, + CLK_PE, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + + DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100), + DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1), + DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1), + DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1), + DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1), + DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1), + DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), + DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + + /* Core Clock Outputs */ + DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), + DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), + DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), + DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), + DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1), + DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1), + DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1), + DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1), + DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1), + + DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074), + DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), + DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c), + + DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), + DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), + DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1), + DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1), + + DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2), + DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), + DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), + DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), + + DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), + DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), + DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), +}; + +static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { + DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C), + DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C), + DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C), + DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C), + DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C), + DEF_MOD("msiof3", 208, R8A77990_CLK_MSO), + DEF_MOD("msiof2", 209, R8A77990_CLK_MSO), + DEF_MOD("msiof1", 210, R8A77990_CLK_MSO), + DEF_MOD("msiof0", 211, R8A77990_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1), + DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1), + DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1), + + DEF_MOD("cmt3", 300, R8A77990_CLK_R), + DEF_MOD("cmt2", 301, R8A77990_CLK_R), + DEF_MOD("cmt1", 302, R8A77990_CLK_R), + DEF_MOD("cmt0", 303, R8A77990_CLK_R), + DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C), + DEF_MOD("sdif3", 311, R8A77990_CLK_SD3), + DEF_MOD("sdif1", 313, R8A77990_CLK_SD1), + DEF_MOD("sdif0", 314, R8A77990_CLK_SD0), + DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1), + + DEF_MOD("rwdt", 402, R8A77990_CLK_R), + DEF_MOD("intc-ex", 407, R8A77990_CLK_CP), + DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3), + + DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4), + DEF_MOD("drif7", 508, R8A77990_CLK_S3D2), + DEF_MOD("drif6", 509, R8A77990_CLK_S3D2), + DEF_MOD("drif5", 510, R8A77990_CLK_S3D2), + DEF_MOD("drif4", 511, R8A77990_CLK_S3D2), + DEF_MOD("drif3", 512, R8A77990_CLK_S3D2), + DEF_MOD("drif2", 513, R8A77990_CLK_S3D2), + DEF_MOD("drif1", 514, R8A77990_CLK_S3D2), + DEF_MOD("drif0", 515, R8A77990_CLK_S3D2), + DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C), + DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C), + DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C), + DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C), + DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C), + DEF_MOD("thermal", 522, R8A77990_CLK_CP), + DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C), + + DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2), + DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2), + DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1), + DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1), + DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2), + DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2), + DEF_MOD("vspb", 626, R8A77990_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1), + + DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4), + DEF_MOD("csi40", 716, R8A77990_CLK_CSI0), + DEF_MOD("du1", 723, R8A77990_CLK_S2D1), + DEF_MOD("du0", 724, R8A77990_CLK_S2D1), + DEF_MOD("lvds", 727, R8A77990_CLK_S2D1), + + DEF_MOD("vin5", 806, R8A77990_CLK_S1D2), + DEF_MOD("vin4", 807, R8A77990_CLK_S1D2), + DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2), + + DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4), + DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), + DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), + DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), + DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2), + DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2), + DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2), + + DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4), + DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), + DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), + DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), + DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), + DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), + DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), + DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), + DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), + DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), + DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4), + DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), + DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), + DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), + DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), + DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), + DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), + DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), + DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), + DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), + DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), + DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), + DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), +}; + +static const unsigned int r8a77990_crit_mod_clks[] __initconst = { + MOD_CLK_ID(408), /* INTC-AP (GIC) */ +}; + +/* + * CPG Clock Data + */ + +/* + * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 + *-------------------------------------------------------------------- + * 0 48 x 1 x100/4 x100/3 x100/3 + * 1 48 x 1 x100/4 x100/3 x58/3 + */ +#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 100, 3, 100, 3, }, + { 1, 100, 3, 58, 3, }, +}; + +static int __init r8a77990_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + + return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode); +} + +const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a77990_core_clks, + .num_core_clks = ARRAY_SIZE(r8a77990_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a77990_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks), + .num_hw_mod_clks = 12 * 32, + + /* Critical Module Clocks */ + .crit_mod_clks = r8a77990_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks), + + /* Callbacks */ + .init = r8a77990_cpg_mssr_init, + .cpg_clk_register = rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 2c467f9..49e5106 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -717,6 +717,12 @@ static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) .data = &r8a77980_cpg_mssr_info, }, #endif +#ifdef CONFIG_CLK_R8A77990 + { + .compatible = "renesas,r8a77990-cpg-mssr", + .data = &r8a77990_cpg_mssr_info, + }, +#endif #ifdef CONFIG_CLK_R8A77995 { .compatible = "renesas,r8a77995-cpg-mssr", diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index efe2a14..642f720 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -143,6 +143,7 @@ struct cpg_mssr_info { extern const struct cpg_mssr_info r8a77965_cpg_mssr_info; extern const struct cpg_mssr_info r8a77970_cpg_mssr_info; extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; +extern const struct cpg_mssr_info r8a77990_cpg_mssr_info; extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;