From patchwork Wed May 23 12:52:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilia Lin X-Patchwork-Id: 10421189 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3248C6016C for ; Wed, 23 May 2018 12:54:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2211E28F97 for ; Wed, 23 May 2018 12:54:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1710128F9D; Wed, 23 May 2018 12:54:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE06128F97 for ; Wed, 23 May 2018 12:54:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932969AbeEWMxa (ORCPT ); Wed, 23 May 2018 08:53:30 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55552 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932960AbeEWMx1 (ORCPT ); Wed, 23 May 2018 08:53:27 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 3F70660F6D; Wed, 23 May 2018 12:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527080006; bh=h7rH1cm5lVVgWTEyaV8PbPdgOLYKNqSFFAbcfS0T/H4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=arp/KekEdJnS5X4BwajrSworAbMY0986uQHiPNZAVkkRUD4lIFR3Z3Q3ilzh1C7j2 L/O/fNJmrHqoJdf9741CRqsIRLy7qvWiv8Qyma0NsO3AJbYdx3JgsG5x7oWbcReMtu 2l8+nWZOF8XKxxfrGEdO3yFf6xF9KQDmFzNMReF0= Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E4BE7602BC; Wed, 23 May 2018 12:53:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527080005; bh=h7rH1cm5lVVgWTEyaV8PbPdgOLYKNqSFFAbcfS0T/H4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pco26ykJDXgPjqMb0JTCNJGQrXme3+FP/VFlSYARPnVDpFmvq2vye0i0b2GjrgZfy zUWgQMTc7oheBgKK+oDaPufzkjgBY7d63bb7WWA9tsmmTP/jEfQVXhtb1AFWCDGXfs WQ7DCqwdPnlmx7Y+i/gK3Jt0uRPdXH4mFADoTJDI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E4BE7602BC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, will.deacon@arm.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vireshk@kernel.org, ilialin@codeaurora.org Subject: [PATCH v11 5/8] dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996 Date: Wed, 23 May 2018 15:52:58 +0300 Message-Id: <1527079981-11179-6-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org> References: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. Signed-off-by: Ilia Lin Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/clock/qcom,kryocc.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt diff --git a/Documentation/devicetree/bindings/clock/qcom,kryocc.txt b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt new file mode 100644 index 0000000..8458783 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kryocc.txt @@ -0,0 +1,17 @@ +Qualcomm CPUSS clock controller for Kryo CPUs +---------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + + "qcom,msm8996-apcc" + +- reg : shall contain base register location and length +- #clock-cells : shall contain 1 + +Example: + kryocc: clock-controller@6400000 { + compatible = "qcom,msm8996-apcc"; + reg = <0x6400000 0x90000>; + #clock-cells = <1>; + };