From patchwork Fri Sep 14 21:48:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601295 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E810A14D6 for ; Fri, 14 Sep 2018 23:07:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF3E828892 for ; Fri, 14 Sep 2018 23:07:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B14332BAF0; Fri, 14 Sep 2018 23:07:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F56A28892 for ; Fri, 14 Sep 2018 23:07:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725832AbeIOEXq (ORCPT ); Sat, 15 Sep 2018 00:23:46 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15257 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725198AbeIOEXq (ORCPT ); Sat, 15 Sep 2018 00:23:46 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 16:06:38 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 16:07:12 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 16:07:12 -0700 Received: from tbergstrom-lnx.Nvidia.com (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 23:07:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 4CAC9F83778; Sat, 15 Sep 2018 00:48:18 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 13/14] memory: tegra: enable Tegra210 EMC scaling driver Date: Sat, 15 Sep 2018 00:48:14 +0300 Message-ID: <1536961695-27809-14-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536966398; bh=nc10B4PWKDv3DKZJ2mbb5VD750yr/i8KBFz91oiKgxM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=Y8Mjc1t4nlW+nur15fd41AwmBttqUwpvkjnnkJ4o15Tee/i99oH7PyI4quYq60IvH bCpFrhtgfpldpw4IVu7AMUc/wVOGZIdZW4BFPK7j6bVU3xWnZlbqQxiMeyN70ieYXz PuEqT8BmruBgh3W7LFPZmDDlGmftshgc0OkfBlx1ZMgURPEmNcDgyiYn6C3SvF2LBd rVXCrIuOAMJqzKfqmqvqLlkLFGc0Cc0Q2KhHEADwqLp7YAlYoURlk8s9L0XMsXOj64 PuyM3V7EXJhtfJNXPWNoT89yk4EwPQu2T0NbScRF6u3Kkr06sb4Hacppto7s3yWSGz qd9mXD0VMGu8A== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Peter De Schrijver --- drivers/memory/tegra/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 6d74e49..456719a 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -15,3 +15,13 @@ config TEGRA124_EMC Tegra124 chips. The EMC controls the external DRAM on the board. This driver is required to change memory timings / clock rate for external memory. + +config TEGRA210_EMC + bool "NVIDIA Tegra210 External Memory Controller driver" + default y + depends on TEGRA_MC && ARCH_TEGRA_210_SOC + help + This driver is for the External Memory Controller (EMC) found on + Tegra210 chips. The EMC controls the external DRAM on the board. + This driver is required to change memory timings / clock rate for + external memory.