From patchwork Fri Sep 14 21:48:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601343 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A95E014DA for ; Sat, 15 Sep 2018 01:27:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89FC02B89B for ; Sat, 15 Sep 2018 01:27:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7DD2F2B8B2; Sat, 15 Sep 2018 01:27:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E3AFC2B89B for ; Sat, 15 Sep 2018 01:27:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726128AbeIOGoK (ORCPT ); Sat, 15 Sep 2018 02:44:10 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:2073 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725754AbeIOGoK (ORCPT ); Sat, 15 Sep 2018 02:44:10 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 18:27:16 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 18:27:12 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 18:27:12 -0700 Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 15 Sep 2018 01:27:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id C83B4F836FB; Sat, 15 Sep 2018 00:48:17 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 02/14] clk: tegra: rename emc timing functions Date: Sat, 15 Sep 2018 00:48:03 +0300 Message-ID: <1536961695-27809-3-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536974836; bh=68txk4/wMf2MKfwuJf6eDKGmF8JPeHPhxgQLx2gXi4A=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=VZgLAxScI6NbqbHIY6ICF3zjbiAxkJ0W2vNpByjRx9dhjzvbvWXMe5kWtykUTYUv5 osdejfcxUswyKnAFfuaWOyKCfpdROwoGAm/HEAb7gA1MrkUFOfFLBySR6HFA7WdXAr by2M1/srPjY9zOO88AmXW4YaxbvrgYfexBCE0O3QgzJfqnxqeZFzrXWD9pjCy1wrhv P5V7DdGXdbsJV08PLAUO8SW1eKSqN0H2JCPBq+5maxKYLuH+lYKofgWZTiLMoBL+Ko XZ2Kn04BnmrVBws1Eng1TMeYO8O0WaKxwzrKJR2G0iCdHBk01DnuchjGRwLPcpTNgD s5SyK7rqSOmuA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra210 emc scaling is similar but sufficiently different to require a new implementation of the clock driver and the emc timing code. Hence rename the existing tegra_emc_prepare_timing_change and tegra_emc_complete_timing_change to tegra124_emc_prepare_timing_change and tegra124_emc_complete_timing_change because they really only apply to Tegra124. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-emc.c | 4 ++-- drivers/memory/tegra/tegra124-emc.c | 8 ++++---- include/soc/tegra/emc.h | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c index 11a5066..ce41d07 100644 --- a/drivers/clk/tegra/clk-emc.c +++ b/drivers/clk/tegra/clk-emc.c @@ -237,7 +237,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, div = timing->parent_rate / (timing->rate / 2) - 2; - err = tegra_emc_prepare_timing_change(emc, timing->rate); + err = tegra124_emc_prepare_timing_change(emc, timing->rate); if (err) return err; @@ -255,7 +255,7 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, spin_unlock_irqrestore(tegra->lock, flags); - tegra_emc_complete_timing_change(emc, timing->rate); + tegra124_emc_complete_timing_change(emc, timing->rate); clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); clk_disable_unprepare(tegra->prev_parent); diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 392dc8d..7140ec8 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -562,8 +562,8 @@ static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, return timing; } -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate) +int tegra124_emc_prepare_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -790,8 +790,8 @@ int tegra_emc_prepare_timing_change(struct tegra_emc *emc, return 0; } -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate) +void tegra124_emc_complete_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h index f6db33b..625f77d 100644 --- a/include/soc/tegra/emc.h +++ b/include/soc/tegra/emc.h @@ -11,9 +11,9 @@ struct tegra_emc; -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate); -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate); +int tegra124_emc_prepare_timing_change(struct tegra_emc *emc, + unsigned long rate); +void tegra124_emc_complete_timing_change(struct tegra_emc *emc, + unsigned long rate); #endif /* __SOC_TEGRA_EMC_H__ */