From patchwork Fri Sep 14 21:48:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601257 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 896FD17D5 for ; Fri, 14 Sep 2018 21:57:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F96D2BCD9 for ; Fri, 14 Sep 2018 21:57:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 63B1D2BCE5; Fri, 14 Sep 2018 21:57:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDC572BCF8 for ; Fri, 14 Sep 2018 21:57:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728297AbeIODNf (ORCPT ); Fri, 14 Sep 2018 23:13:35 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10974 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727473AbeIODNf (ORCPT ); Fri, 14 Sep 2018 23:13:35 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 14:57:16 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 14:57:13 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 14:57:13 -0700 Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 21:57:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id D41C0F8370F; Sat, 15 Sep 2018 00:48:17 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 03/14] clk: tegra: emc: simplify parent matching Date: Sat, 15 Sep 2018 00:48:04 +0300 Message-ID: <1536961695-27809-4-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL108.nvidia.com (172.18.146.13) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536962236; bh=I70W2ffNvJbDXN+gOzlg86sBqNd64wiRXF4oM83uwFg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=OPt/hxhqd/hTYYphD18Wh/T3d9QTmCxEGuA9Dv+T4EOI/9g86yDObRADyhAeh/Tc8 /UHOCMEkdpS7gMNFP1iiFOB6FpT/kANQcbAQ/HqWThkF2w7bfQa8w3HHHI7WN9r3jq +/XmTFLI84yc1KRtKPh+ulnA9M7T5Tb0BueqA4O5OEg7ka3Ow8CaB+uBgdFKPKipig px35DofQt4Irl3sgodLn0AnI+ijVod1zqxfG+R/6ENm3AbDIulcl4vVrV95xAoyifx hGx35tEJ21Se6U/dc3YDeOijZZHxyrAuPeU/JT7IXyx8FPrxXlYwoefj6V9UQtuH+X oMglnZtbLE8bQ== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can't change the rate of a parent clock source when that clock source in use. However pll_m_ud and pll_c_ud are just low jitter paths to the same clock source, so when comparing clock sources we should treat those as the same source. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-emc.c | 61 ++++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c index ce41d07..e836a9b 100644 --- a/drivers/clk/tegra/clk-emc.c +++ b/drivers/clk/tegra/clk-emc.c @@ -49,24 +49,10 @@ "pll_c2", "pll_c3", "pll_c_ud" }; -/* - * List of clock sources for various parents the EMC clock can have. - * When we change the timing to a timing with a parent that has the same - * clock source as the current parent, we must first change to a backup - * timing that has a different clock source. - */ - -#define EMC_SRC_PLL_M 0 -#define EMC_SRC_PLL_C 1 -#define EMC_SRC_PLL_P 2 -#define EMC_SRC_CLK_M 3 -#define EMC_SRC_PLL_C2 4 -#define EMC_SRC_PLL_C3 5 - -static const char emc_parent_clk_sources[] = { - EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M, - EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C -}; +#define TEGRA124_EMC_PARENT_PLL_M 0 +#define TEGRA124_EMC_PARENT_PLL_M_UD 4 +#define TEGRA124_EMC_PARENT_PLL_C 1 +#define TEGRA124_EMC_PARENT_PLL_C_UD 7 struct emc_timing { unsigned long rate, parent_rate; @@ -266,6 +252,22 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, return 0; } +static int normalize_parent_idx(int parent_idx) +{ + switch (parent_idx) { + case TEGRA124_EMC_PARENT_PLL_M: + case TEGRA124_EMC_PARENT_PLL_M_UD: + return TEGRA124_EMC_PARENT_PLL_M; + + case TEGRA124_EMC_PARENT_PLL_C: + case TEGRA124_EMC_PARENT_PLL_C_UD: + return TEGRA124_EMC_PARENT_PLL_C:; + + default: + return parent_idx; + } +} + /* * Get backup timing to use as an intermediate step when a change between * two timings with the same clock source has been requested. First try to @@ -275,18 +277,20 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra, int timing_index) { - int i; + int i, new_parent_idx; u32 ram_code = tegra_read_ram_code(); struct emc_timing *timing; + new_parent_idx = tegra->timings[timing_index].parent_index; + new_parent_idx = normalize_parent_idx(new_parent_idx); + for (i = timing_index+1; i < tegra->num_timings; i++) { timing = tegra->timings + i; if (timing->ram_code != ram_code) continue; - if (emc_parent_clk_sources[timing->parent_index] != - emc_parent_clk_sources[ - tegra->timings[timing_index].parent_index]) + if (normalize_parent_idx(timing->parent_index) + != new_parent_idx) return timing; } @@ -295,9 +299,8 @@ static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra, if (timing->ram_code != ram_code) continue; - if (emc_parent_clk_sources[timing->parent_index] != - emc_parent_clk_sources[ - tegra->timings[timing_index].parent_index]) + if (normalize_parent_idx(timing->parent_index) + != new_parent_idx) return timing; } @@ -309,7 +312,7 @@ static int emc_set_rate(struct clk_hw *hw, unsigned long rate, { struct tegra_clk_emc *tegra; struct emc_timing *timing = NULL; - int i, err; + int i, err, new_parent_idx, cur_parent_idx; u32 ram_code = tegra_read_ram_code(); tegra = container_of(hw, struct tegra_clk_emc, hw); @@ -338,8 +341,10 @@ static int emc_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; } - if (emc_parent_clk_sources[emc_get_parent(hw)] == - emc_parent_clk_sources[timing->parent_index] && + cur_parent_idx = normalize_parent_idx(emc_get_parent(hw)); + new_parent_idx = normalize_parent_idx(timing->parent_index); + + if (cur_parent_idx == new_parent_idx && clk_get_rate(timing->parent) != timing->parent_rate) { /* * Parent clock source not changed but parent rate has changed,