From patchwork Fri Sep 14 21:48:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1201514DB for ; Fri, 14 Sep 2018 21:57:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E96E02BCD9 for ; Fri, 14 Sep 2018 21:57:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DB7912BCF4; Fri, 14 Sep 2018 21:57:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5BA912BCD9 for ; Fri, 14 Sep 2018 21:57:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727774AbeIODNe (ORCPT ); Fri, 14 Sep 2018 23:13:34 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10973 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727473AbeIODNe (ORCPT ); Fri, 14 Sep 2018 23:13:34 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 14:57:16 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 14:57:13 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 14:57:13 -0700 Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 21:57:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id EB6C8F8372A; Sat, 15 Sep 2018 00:48:17 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 05/14] memory: tegra: mc: Introduce helpers Date: Sat, 15 Sep 2018 00:48:06 +0300 Message-ID: <1536961695-27809-6-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL108.nvidia.com (172.18.146.13) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536962236; bh=olr11uPYLnOjwwIM8/Vh89Mm++eb/3wdXm1DUThfwJY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=UQbOui/6i5ZRpGGD3arVYx73zWqGRjbfgvUS1cERq2N8gGrdFUuAyeMmn9DKI0Qxa kDlzELi21Q9RM3BotAw+pXlAfDL7VTAXaA0ZahwXwVzRGthTAfjTOSmBiSUwMl5OMR vAn7RL7JQpQT2b3vjiGSqGclU5oak3izPx2iQC4qHPPJSxatFO5H6arnqHL/wVyIle G6izEhBBQ2ACvd6GnH133+2TLIkAHc49LbRlxDDb1D2hZzKYzgd2LvWrNbYcRFXT+q Xo8QHwKoLiYDWeAUiwAk+eaz4G+u8J9SoOiL6OdEizPvF34jZodN6fbJ8XtHzxLyCv XGP0u4TzX5LPg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Introduce a few helper functions to lookup a timing for a given rate and modify MC register field. These will be useful when adding support for updating the latency allowance (LA) registers when scaling the EMC clock. Signed-off-by: Peter De Schrijver --- drivers/memory/tegra/mc.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a4803ac..af4bf29 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -73,6 +73,17 @@ }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); +static void mc_modifyl(struct tegra_mc *mc, u32 reg, u32 value, u8 shift, + u8 mask) +{ + u32 val; + + val = readl(mc->regs + reg); + val &= ~(mask << shift); + val |= (value & mask) << shift; + writel(val, mc->regs + reg); +} + static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) { unsigned long long tick; @@ -91,18 +102,14 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) /* write latency allowance defaults */ for (i = 0; i < mc->soc->num_clients; i++) { const struct tegra_mc_la *la = &mc->soc->clients[i].la; - u32 value; - - value = readl(mc->regs + la->reg); - value &= ~(la->mask << la->shift); - value |= (la->def & la->mask) << la->shift; - writel(value, mc->regs + la->reg); + mc_modifyl(mc, la->reg, la->def, la->shift, la->mask); } return 0; } -void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) +static struct tegra_mc_timing *find_mc_timing(struct tegra_mc *mc, + unsigned long rate) { unsigned int i; struct tegra_mc_timing *timing = NULL; @@ -114,6 +121,15 @@ void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) } } + return timing; +} + +void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) +{ + unsigned int i; + struct tegra_mc_timing *timing = NULL; + + timing = find_mc_timing(mc, rate); if (!timing) { dev_err(mc->dev, "no memory timing registered for rate %lu\n", rate);