From patchwork Fri Sep 14 21:48:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601263 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05FB417D5 for ; Fri, 14 Sep 2018 22:07:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DCDA32BBB8 for ; Fri, 14 Sep 2018 22:07:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D175F2BCA6; Fri, 14 Sep 2018 22:07:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6B82D2BCA3 for ; Fri, 14 Sep 2018 22:07:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727838AbeIODXg (ORCPT ); Fri, 14 Sep 2018 23:23:36 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:12067 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727473AbeIODXg (ORCPT ); Fri, 14 Sep 2018 23:23:36 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 15:06:38 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 15:07:12 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 15:07:12 -0700 Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 22:07:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 0303EF8372F; Sat, 15 Sep 2018 00:48:18 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 06/14] memory: tegra: mc: Add support for scaled LA Date: Sat, 15 Sep 2018 00:48:07 +0300 Message-ID: <1536961695-27809-7-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536962798; bh=XAVViav3/7ARLCn4rDRnbN6nryLEYGtPqE7tbIuUWmE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=Texd/WZ3Jv5uNz0Q3NZPuDfcOT6KrexYAkSlCAWHehbGV0ITODd3qb3WRx5MI6V6q gTpnpKgI83A2Jcd5IUOqPNArcjEilXtIb1jaTVseTmP5EmRmT2YeDvOm74jeW9obef IxTkaor/NPOzCHQQQtWdlSoO8eSvWk0J8mGCmJrRWDy8kuYYVhVzK9hWhR9p3mwhgB 9g+ig1u9scTv6wQowyLJeFjZ8Hv4pc39rstoJ1W8IRT5OvHgPUBGD0LqufNVArtVsF bEtInrCC6SzcewSZRxB9PpghmuXCJAjpbfXJ+ZPPCjq/gELmd8erDvKjajkOtUlvry JrrPrJink11OA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Besides for each memory client, Tegra210 also has a number of 'scaled latency allowance' registers. Add support for them. Signed-off-by: Peter De Schrijver --- drivers/memory/tegra/mc.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++ include/soc/tegra/mc.h | 6 ++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index af4bf29..a7ed8e1 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -138,6 +138,38 @@ void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) for (i = 0; i < mc->soc->num_emem_regs; ++i) mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); + +} + +void tegra_mc_write_scaled_la_configuration(struct tegra_mc *mc, + unsigned long rate) +{ + unsigned int i, idx; + struct tegra_mc_timing *timing = NULL; + + if (!mc->soc->has_scaled_la) + return; + + timing = find_mc_timing(mc, rate); + if (!timing) { + dev_err(mc->dev, "no memory timing registered for rate %lu\n", + rate); + return; + } + + idx = 0; + for (i = 0; i < mc->soc->num_clients; i++) { + const struct tegra_mc_la *la = &mc->soc->clients[i].la; + mc_modifyl(mc, la->reg, timing->scaled_la_data[idx++], + la->shift, la->mask); + } + + for (i = 0; i < mc->soc->num_scaled_la_regs; i++) { + mc_modifyl(mc, mc->soc->scaled_la_regs[i], + timing->scaled_la_data[idx++], 0, 0xff); + mc_modifyl(mc, mc->soc->scaled_la_regs[i], + timing->scaled_la_data[idx++], 16, 0xff); + } } unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) @@ -181,6 +213,28 @@ static int load_one_timing(struct tegra_mc *mc, return err; } + if (mc->soc->has_scaled_la) { + unsigned int num_scaled_la_regs; + + num_scaled_la_regs = mc->soc->num_clients; + /* each scaled LA register has a HI and a LO allowance value */ + num_scaled_la_regs += mc->soc->num_scaled_la_regs * 2; + timing->scaled_la_data = devm_kcalloc(mc->dev, + num_scaled_la_regs, sizeof(u8), GFP_KERNEL); + if (!timing->scaled_la_data) + return -ENOMEM; + + err = of_property_read_u8_array(node, + "nvidia,scale-la-configuration", + timing->scaled_la_data, num_scaled_la_regs); + if (err) { + dev_err(mc->dev, + "timing %s: failed to read scaled LA configuration\n", + node->name); + return err; + } + } + return 0; } diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 44202ff..fce457c 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -24,6 +24,7 @@ struct tegra_mc_timing { unsigned long rate; u32 *emem_data; + u8 *scaled_la_data; }; /* latency allowance */ @@ -93,12 +94,16 @@ struct tegra_mc_soc { const unsigned long *emem_regs; unsigned int num_emem_regs; + const unsigned long *scaled_la_regs; + unsigned int num_scaled_la_regs; + unsigned int num_address_bits; unsigned int atom_size; u8 client_id_mask; const struct tegra_smmu_soc *smmu; + bool has_scaled_la; }; struct tegra_mc { @@ -117,5 +122,6 @@ struct tegra_mc { void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc); +void tegra_mc_write_scaled_la_configuration(struct tegra_mc *mc, unsigned long rate); #endif /* __SOC_TEGRA_MC_H__ */