From patchwork Wed Jan 16 18:37:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10766773 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33B2D1390 for ; Wed, 16 Jan 2019 18:39:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 20B2C2B48B for ; Wed, 16 Jan 2019 18:39:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 11D952CE71; Wed, 16 Jan 2019 18:39:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB93E2B48B for ; Wed, 16 Jan 2019 18:39:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729210AbfAPSjO (ORCPT ); Wed, 16 Jan 2019 13:39:14 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:31084 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729056AbfAPSjO (ORCPT ); Wed, 16 Jan 2019 13:39:14 -0500 X-IronPort-AV: E=Sophos;i="5.56,487,1539615600"; d="scan'208";a="5355899" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 17 Jan 2019 03:39:12 +0900 Received: from fabrizio-dev.ree.adwin.renesas.com (unknown [10.226.37.13]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 03A6740F1461; Thu, 17 Jan 2019 03:39:05 +0900 (JST) From: Fabrizio Castro To: Rob Herring , Mark Rutland , Wolfgang Grandegger , Marc Kleine-Budde , Michael Turquette , Stephen Boyd Cc: Fabrizio Castro , Simon Horman , Magnus Damm , "David S. Miller" , Geert Uytterhoeven , Thierry Reding , =?utf-8?q?Andreas_F=C3=A4rber?= , Alexandre Belloni , Kevin Hilman , Johan Hovold , Lukasz Majewski , Michal Simek , =?utf-8?b?TWljaGFsIFZva8OhxI0=?= , Martin Blumenstingl , Ben Whitten , Chris Paterson , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-clk@vger.kernel.org, Biju Das , linux-kernel@vger.kernel.org, ebiharaml@si-linux.co.jp Subject: [PATCH 09/11] dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks Date: Wed, 16 Jan 2019 18:37:52 +0000 Message-Id: <1547663874-29411-10-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1547663874-29411-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1547663874-29411-1-git-send-email-fabrizio.castro@bp.renesas.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to the latest information, the clock options for CAN on RZ/G2 are the same as the ones available on R-Car Gen3 Fixes: 868b7c0f43e6 ("dt-bindings: can: rcar_can: Add r8a774a1 support") Signed-off-by: Fabrizio Castro Reviewed-by: Chris Paterson Reviewed-by: Simon Horman Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/net/can/rcar_can.txt | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt index 7fcf501..b463e12 100644 --- a/Documentation/devicetree/bindings/net/can/rcar_can.txt +++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt @@ -28,13 +28,8 @@ Required properties: - reg: physical base address and size of the R-Car CAN register map. - interrupts: interrupt specifier for the sole interrupt. -- clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2 - devices. - phandles and clock specifiers for 3 CAN clock inputs for every other - SoC. -- clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk". - 3 clock input name strings for every other SoC: "clkp1", "clkp2", - "can_clk". +- clocks: phandles and clock specifiers for 3 CAN clock inputs. +- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk". - pinctrl-0: pin control group to be used for this controller. - pinctrl-names: must be "default". @@ -50,8 +45,7 @@ using the below properties: Optional properties: - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are: <0x0> (default) : Peripheral clock (clkp1) - <0x1> : Peripheral clock (clkp2) (not supported by - RZ/G2 devices) + <0x1> : Peripheral clock (clkp2) <0x3> : External input clock Example