| Message ID | 1553254384-8196-1-git-send-email-gareth.williams.jx@renesas.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: renesas: r9a06g032: Add missing PCI USB clock | expand |
On Fri, Mar 22, 2019 at 12:35 PM Gareth Williams <gareth.williams.jx@renesas.com> wrote: > The clock driver is missing support for the clk_pci_usb clock that is > present on the SoC. This is added to allow the clock to be supported. > > Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. queueing clk-renesas-for-v5.2. Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 5d7f77b1..0b492b5 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -198,6 +198,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = { D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0), D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0), D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0), + D_GATE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0), D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0), D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0), D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
The clock driver is missing support for the clk_pci_usb clock that is present on the SoC. This is added to allow the clock to be supported. Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> --- drivers/clk/renesas/r9a06g032-clocks.c | 1 + 1 file changed, 1 insertion(+)