From patchwork Mon Aug 8 17:21:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9268939 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2B3336075A for ; Mon, 8 Aug 2016 17:22:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B25B27F95 for ; Mon, 8 Aug 2016 17:22:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0FC4D283A6; Mon, 8 Aug 2016 17:22:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 726F527F95 for ; Mon, 8 Aug 2016 17:22:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752592AbcHHRV4 (ORCPT ); Mon, 8 Aug 2016 13:21:56 -0400 Received: from foss.arm.com ([217.140.101.70]:37100 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752265AbcHHRUz (ORCPT ); Mon, 8 Aug 2016 13:20:55 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6764043E; Mon, 8 Aug 2016 10:22:21 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7E61D3F459; Mon, 8 Aug 2016 10:20:53 -0700 (PDT) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: linux-sunxi@googlegroups.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Emilio=20L=C3=B3pez?= , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH v4 3/7] clk: sunxi: add generic multi-parent bus clock gates driver Date: Mon, 8 Aug 2016 18:21:45 +0100 Message-Id: <20160808172149.30861-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160808172149.30861-1-andre.przywara@arm.com> References: <20160808172149.30861-1-andre.przywara@arm.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Allwinner H3 SoC introduced bus clock gates with potentially different parents per clock gate register. The H3 driver chose to hardcode the actual parent clock relation in the code. Add a new driver (which has the potential to drive the H3 and also the simple clock gates as well) which uses the power of DT to describe this relationship in an elegant and flexible way. Using one subnode for every parent clock we get away with a single DT compatible match, which can be used as a fallback value in the actual DTs without the need to add specific compatible strings to the code. This avoids adding a new driver or function for every new SoC. Signed-off-by: Andre Przywara Acked-by: Jean-Francois Moine --- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-multi-gates.c | 105 ++++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 drivers/clk/sunxi/clk-multi-gates.c diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 39d2044..caf2bf6 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -14,6 +14,7 @@ obj-y += clk-simple-gates.o obj-y += clk-sun4i-display.o obj-y += clk-sun4i-pll3.o obj-y += clk-sun4i-tcon-ch1.o +obj-y += clk-multi-gates.o obj-y += clk-sun8i-bus-gates.o obj-y += clk-sun8i-mbus.o obj-y += clk-sun9i-core.o diff --git a/drivers/clk/sunxi/clk-multi-gates.c b/drivers/clk/sunxi/clk-multi-gates.c new file mode 100644 index 0000000..76e715a --- /dev/null +++ b/drivers/clk/sunxi/clk-multi-gates.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * Based on clk-sun8i-bus-gates.c, which is: + * Copyright (C) 2015 Jens Kuske + * Based on clk-simple-gates.c, which is: + * Copyright 2015 Maxime Ripard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(gates_lock); + +static void __init sunxi_parse_parent(struct device_node *node, + struct clk_onecell_data *clk_data, + void __iomem *reg) +{ + const char *parent = of_clk_get_parent_name(node, 0); + const char *clk_name; + struct property *prop; + struct clk *clk; + const __be32 *p; + int index, i = 0; + + of_property_for_each_u32(node, "clock-indices", prop, p, index) { + of_property_read_string_index(node, "clock-output-names", + i, &clk_name); + + clk = clk_register_gate(NULL, clk_name, parent, 0, + reg + 4 * (index / 32), index % 32, + 0, &gates_lock); + i++; + if (IS_ERR(clk)) { + pr_warn("could not register gate clock \"%s\"\n", + clk_name); + continue; + } + if (clk_data->clks[index]) + pr_warn("bus-gate clock %s: index #%d already registered as %s\n", + clk_name, index, "?"); + else + clk_data->clks[index] = clk; + } +} + +static void __init sunxi_multi_bus_gates_init(struct device_node *node) +{ + struct clk_onecell_data *clk_data; + struct device_node *child; + struct property *prop; + struct resource res; + void __iomem *reg; + const __be32 *p; + int number = 0; + int index; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + if (IS_ERR(reg)) + return; + + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); + if (!clk_data) + goto err_unmap; + + for_each_child_of_node(node, child) + of_property_for_each_u32(child, "clock-indices", prop, p, index) + number = max(number, index); + + clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); + if (!clk_data->clks) + goto err_free_data; + + for_each_child_of_node(node, child) + sunxi_parse_parent(child, clk_data, reg); + + clk_data->clk_num = number + 1; + if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) + pr_err("registering bus-gate clock %s failed\n", node->name); + + return; + +err_free_data: + kfree(clk_data); +err_unmap: + iounmap(reg); + of_address_to_resource(node, 0, &res); + release_mem_region(res.start, resource_size(&res)); +} + +CLK_OF_DECLARE(sunxi_multi_bus_gates, "allwinner,sunxi-multi-bus-gates-clk", + sunxi_multi_bus_gates_init);