From patchwork Tue Feb 28 18:12:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 9597227 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D2E8560414 for ; Wed, 1 Mar 2017 00:30:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C49372833C for ; Wed, 1 Mar 2017 00:30:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B9323283E8; Wed, 1 Mar 2017 00:30:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DB3E2833C for ; Wed, 1 Mar 2017 00:30:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751640AbdCAAaB (ORCPT ); Tue, 28 Feb 2017 19:30:01 -0500 Received: from gloria.sntech.de ([95.129.55.99]:40194 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751099AbdCAA37 (ORCPT ); Tue, 28 Feb 2017 19:29:59 -0500 Received: from [104.132.0.100] (helo=phil.google.com) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1cimGI-0007SV-IJ; Tue, 28 Feb 2017 19:12:34 +0100 From: Heiko Stuebner To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-rockchip@lists.infradead.org, linux-clk@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 2/2] clk: rockchip: Make uartpll a child of the gpll on rk3036 Date: Tue, 28 Feb 2017 19:12:14 +0100 Message-Id: <20170228181214.6413-3-heiko@sntech.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170228181214.6413-1-heiko@sntech.de> References: <20170228181214.6413-1-heiko@sntech.de> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The shared uart-pll is on boot a child of the apll that can get changed by cpu frequency scaling. So move it away to the more stable gpll to make sure the uart doesn't break on cpu frequency changes. This turned up during the 4.11 merge-window when commit 6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used") added general termios enablement making the uart on rk3036 change frequency and thus making it susceptible for the frequency scaling issue. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3036.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index dcde70f4c105..8b8d2c90c884 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -442,7 +443,7 @@ static void __init rk3036_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; - struct clk *clk; + struct clk *clk, *clk2; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -480,6 +481,19 @@ static void __init rk3036_clk_init(struct device_node *np) rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); + clk = __clk_lookup("uart_pll_clk"); + clk2 = __clk_lookup("gpll"); + if (clk && clk2) { + int ret = clk_set_parent(clk, clk2); + + if (ret < 0) + pr_warn("%s: could not reparent uart_pll_clk to gpll\n", + __func__); + } else { + pr_warn("%s: missing clocks to reparent uart_pll_clk to gpll\n", + __func__); + } + rockchip_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);