From patchwork Fri Mar 17 17:18:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 9631089 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CA7B260245 for ; Fri, 17 Mar 2017 17:19:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B5E50286E7 for ; Fri, 17 Mar 2017 17:19:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AAAE1286F5; Fri, 17 Mar 2017 17:19:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 32748286F0 for ; Fri, 17 Mar 2017 17:19:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751210AbdCQRTZ (ORCPT ); Fri, 17 Mar 2017 13:19:25 -0400 Received: from gloria.sntech.de ([95.129.55.99]:53714 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751107AbdCQRTW (ORCPT ); Fri, 17 Mar 2017 13:19:22 -0400 Received: from p5b127f36.dip0.t-ipconnect.de ([91.18.127.54] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1covWm-0004v9-Lj; Fri, 17 Mar 2017 18:19:00 +0100 From: Heiko Stuebner To: linux-rockchip@lists.infradead.org Cc: linus.walleij@linaro.org, robh+dt@kernel.org, andy.yan@rock-chips.com, sboyd@codeaurora.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-clk@vger.kernel.org, mturquette@baylibre.com, Heiko Stuebner Subject: [PATCH v2 1/6] dt-bindings: rockchip, pinctrl: rename RK1108 to RV1108 Date: Fri, 17 Mar 2017 18:18:35 +0100 Message-Id: <20170317171840.4683-2-heiko@sntech.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170317171840.4683-1-heiko@sntech.de> References: <20170317171840.4683-1-heiko@sntech.de> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andy Yan Rockchip finally named the SOC as RV1108, so change it. Also move the compatible list to one compatible per line. Signed-off-by: Andy Yan Acked-by: Rob Herring Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 403b5a272f56..ee01ab58224d 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -19,11 +19,18 @@ The pins are grouped into up to 5 individual pin banks which need to be defined as gpio sub-nodes of the pinmux controller. Required properties for iomux controller: - - compatible: one of "rockchip,rk1108-pinctrl", "rockchip,rk2928-pinctrl" - "rockchip,rk3066a-pinctrl", "rockchip,rk3066b-pinctrl" - "rockchip,rk3188-pinctrl", "rockchip,rk3228-pinctrl" - "rockchip,rk3288-pinctrl", "rockchip,rk3328-pinctrl" - "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl" + - compatible: should be + "rockchip,rv1108-pinctrl": for Rockchip RV1108 + "rockchip,rk2928-pinctrl": for Rockchip RK2928 + "rockchip,rk3066a-pinctrl": for Rockchip RK3066a + "rockchip,rk3066b-pinctrl": for Rockchip RK3066b + "rockchip,rk3188-pinctrl": for Rockchip RK3188 + "rockchip,rk3228-pinctrl": for Rockchip RK3228 + "rockchip,rk3288-pinctrl": for Rockchip RK3288 + "rockchip,rk3328-pinctrl": for Rockchip RK3328 + "rockchip,rk3368-pinctrl": for Rockchip RK3368 + "rockchip,rk3399-pinctrl": for Rockchip RK3399 + - rockchip,grf: phandle referencing a syscon providing the "general register files"