clk: bcm2835: Correct the prediv logic

Commit Message

Eric Anholt May 15, 2017, 5:35 p.m. UTC

From: Phil Elwell <[e-mail]>

If a clock has the prediv flag set, both the integer and fractional
parts must be scaled when calculating the resulting frequency.

Signed-off-by: Phil Elwell <[e-mail]>
Signed-off-by: Eric Anholt <[e-mail]>
---

While this is a bugfix, I haven't put a "Fixes:" line in here to get
it automatically backported to stable.  We had trouble with the
out-of-tree DSI panel driver, at least: Our old set_rate() didn't
work, because the new PLL was just barely too fast to get the integer
PLL divider we needed.  We may run into similar troubles
elsewhere. --anholt

 drivers/clk/bcm/clk-bcm2835.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Stefan Wahren May 15, 2017, 5:47 p.m. UTC | #1

Hi Eric,

> Eric Anholt <[e-mail]> hat am 15. Mai 2017 um 19:35 geschrieben:
> 
> 
> From: Phil Elwell <[e-mail]>
> 
> If a clock has the prediv flag set, both the integer and fractional
> parts must be scaled when calculating the resulting frequency.
> 
> Signed-off-by: Phil Elwell <[e-mail]>
> Signed-off-by: Eric Anholt <[e-mail]>
> ---
> 
> While this is a bugfix, I haven't put a "Fixes:" line in here to get
> it automatically backported to stable.  

sorry, i can't follow. How should this happen without "Fixes: "?

> We had trouble with the
> out-of-tree DSI panel driver, at least: Our old set_rate() didn't
> work, because the new PLL was just barely too fast to get the integer
> PLL divider we needed.  We may run into similar troubles
> elsewhere. --anholt
>
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Eric Anholt May 15, 2017, 7:03 p.m. UTC | #2

Stefan Wahren <[e-mail]> writes:

> Hi Eric,
>
>> Eric Anholt <[e-mail]> hat am 15. Mai 2017 um 19:35 geschrieben:
>> 
>> 
>> From: Phil Elwell <[e-mail]>
>> 
>> If a clock has the prediv flag set, both the integer and fractional
>> parts must be scaled when calculating the resulting frequency.
>> 
>> Signed-off-by: Phil Elwell <[e-mail]>
>> Signed-off-by: Eric Anholt <[e-mail]>
>> ---
>> 
>> While this is a bugfix, I haven't put a "Fixes:" line in here to get
>> it automatically backported to stable.  
>
> sorry, i can't follow. How should this happen without "Fixes: "?

I didn't want it to be backported to stable, because of the risk.

Stephen Boyd June 2, 2017, 10:41 p.m. UTC | #3

On 05/15, Eric Anholt wrote:
> From: Phil Elwell <[e-mail]>
> 
> If a clock has the prediv flag set, both the integer and fractional
> parts must be scaled when calculating the resulting frequency.
> 
> Signed-off-by: Phil Elwell <[e-mail]>
> Signed-off-by: Eric Anholt <[e-mail]>
> ---

Applied to clk-next

Patch

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 025853870619..7a35df6b45bd 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -616,8 +616,10 @@  static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
 	using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
 		data->ana->fb_prediv_mask;
 
-	if (using_prediv)
+	if (using_prediv) {
 		ndiv *= 2;
+		fdiv *= 2;
+	}
 
 	return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
 }