From patchwork Wed Jun 7 20:04:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 9772751 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B4DCD60350 for ; Wed, 7 Jun 2017 20:13:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B442284EA for ; Wed, 7 Jun 2017 20:13:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8FEB02852A; Wed, 7 Jun 2017 20:13:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21C41284EA for ; Wed, 7 Jun 2017 20:13:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751437AbdFGUN4 (ORCPT ); Wed, 7 Jun 2017 16:13:56 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:57800 "EHLO outils.crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751413AbdFGUN4 (ORCPT ); Wed, 7 Jun 2017 16:13:56 -0400 X-Greylist: delayed 549 seconds by postgrey-1.27 at vger.kernel.org; Wed, 07 Jun 2017 16:13:55 EDT From: Paul Cercueil To: Ralf Baechle , Michael Turquette , Stephen Boyd , Rob Herring Cc: Paul Burton , Maarten ter Huurne , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-clk@vger.kernel.org, Paul Cercueil Subject: [PATCH 02/15] clk: ingenic: support PLLs with no bypass bit Date: Wed, 7 Jun 2017 22:04:26 +0200 Message-Id: <20170607200439.24450-3-paul@crapouillou.net> In-Reply-To: <20170607200439.24450-1-paul@crapouillou.net> References: <20170607200439.24450-1-paul@crapouillou.net> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The second PLL of the JZ4770 does not have a bypass bit. This commit makes it possible to support it with the current common CGU code. Signed-off-by: Paul Cercueil --- drivers/clk/ingenic/cgu.c | 3 ++- drivers/clk/ingenic/cgu.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index eb9002ccf3fc..75b083ba294c 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -100,7 +100,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) n += pll_info->n_offset; od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); - bypass = !!(ctl & BIT(pll_info->bypass_bit)); + bypass = !pll_info->no_bypass_bit && + !!(ctl & BIT(pll_info->bypass_bit)); enable = !!(ctl & BIT(pll_info->enable_bit)); if (bypass) diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 09700b2c555d..2e3d258c3ed2 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -48,6 +48,7 @@ * @bypass_bit: the index of the bypass bit in the PLL control register * @enable_bit: the index of the enable bit in the PLL control register * @stable_bit: the index of the stable bit in the PLL control register + * @no_bypass_bit: if set, the PLL has no bypass functionality */ struct ingenic_cgu_pll_info { unsigned reg; @@ -58,6 +59,7 @@ struct ingenic_cgu_pll_info { u8 bypass_bit; u8 enable_bit; u8 stable_bit; + bool no_bypass_bit; }; /**